System with meshed power and signal buses on cell array

A semiconductor memory comprising:

• a plurality of first regions arranged in lattice fashion each of which corresponds to a memory array including a plurality of main word lines extending in a first direction, a plurality of sets of sub-word lines extending in said first direction, a plurality of data lines extending in a second direction perpendicular to said first direction and a plurality of memory cells each of which is coupled to a corresponding one of said plurality of subword lines and a corresponding one of said data lines, one of said plurality of main word lines being allotted to one of said plurality of sets of subword lines;
• a plurality of second regions, each of which is arranged alternately with each of said first regions arranged along said first direction;
• a plurality of third regions, each of which is arranged alternately with each of said first regions arranged along said second direction and includes sense amplifiers connected to said data lines;
• a plurality of fourth regions, each of which is arranged alternately with each of said third regions arranged along said first direction;
• first, second, third and fourth decoders which are included in said plurality of second regions;
• and
• first, second, third and fourth drivers which are included in said plurality of fourth regions,
• wherein first main word line is allotted to first, second, third and fourth subword lines in one of said first regions,
• wherein said first and second subword lines are connected to output terminals of said first and second decoders, respectively,
• wherein said third and fourth subword lines are connected to output terminals of said third and fourth decoders, respectively,
• wherein said first and second decoders are separated from said third and fourth decoders across said one of first regions,
• wherein said first driver is separated from said second driver across a second region in which said first and second decoders are included,
• wherein said third driver is separated from said fourth driver across a second region in which said third and fourth decoders are included,
• wherein each of first input terminals of said first, second, third and fourth decoders are connected to a main word line,
• wherein said first driver, connected to a second input terminal of said first decoder, outputting selection level voltage to be supplied to said first subword line;
• wherein said second driver, connected to a second input terminal of said second decoder, outputting selection level voltage to be supplied to said second subword line,
• wherein said third driver, connected to a second input terminal of said third decoder, outputting selection level voltage to be supplied to said third subword line,
• wherein said fourth driver, connected to a second input terminal of said fourth decoder, outputting selection level voltage to be supplied to said fourth subword line.