Semiconductor memory mounted with cache memory

Abstract

A semiconductor integrated circuit device includes a synchronous burst memory circuit section capable of performing an address pipeline operation and a register array section constituting a cache memory in an address space of the memory circuit section. The register array section includes a tag register array and a data register array. Address signals, which are to be supplied to a memory cell array in the memory circuit section, are distributed to a tag address and a cache address of the tag register array. The cache address is supplied to the data register array.

Dependencies are inferred from the claim text.