Multiple layer printed circuit board having power planes on outer layers

A multiple layer printed circuit board comprising:

• a first intermediate conductive layer having conductive interconnect traces formed therein;
• a first outer conductive layer located above the first intermediate conductive layer and separated from the first intermediate conductive layer by a first dielectric layer;
• a second outer conductive layer located below the first intermediate conductive layer and separated from the first intermediate conductive layer by a second dielectric layer, wherein the first outer conductive layer is coupled to a first power supply voltage to provide a first power supply conductive plate, and the second outer conductive layer is coupled to a second power supply voltage to provide a second power supply conductive plate;
• and
• a solder mask located on a top surface of the first outer conductive layer, the solder mask having first openings located in regions of the printed circuit board not intended to be populated such that the second openings expose the first outer conductive layer to provide heat dissipation openings.

A printed circuit board comprising:

• an outer conductive layer to carry a power supply voltage, the outer conductive layer being on a first side of the printed circuit board and having a plurality of mounting pads electrically isolated therein, each of the plurality of mounting pads including:
• a first conductive region sized to accept a circuit device intended to be soldered to the mounting pad, wherein the first conductive region is located beneath the circuit device when the circuit device is soldered to the mounting pad;
• a second conductive region, which is integral with the first conductive region, the second conductive region is located laterally outside of the circuit device when the circuit device is soldered to the mounting pad, such that the second conductive region provides a solder fillet area;
• and
• a plated via located in the first conductive region and extending downwardly through the mounting pad for electrical interconnection with conductive regions located below the mounting pad.

A method of fabricating a printed circuit board, the method comprising:

• providing a first dielectric layer;
• fabricating a conductive interconnect layer on a bottom surface of the first dielectric layer, the first conductive interconnect layer having interconnect traces formed therein;
• fabricating a conductive power plane layer on a top surface of the first dielectric layer;
• defining mounting pads in the conductive power plane layer, each mounting pad as a first region for receiving an electronic component, such that the first region is located beneath the electronic component when the electronic component is coupled to the mounting pads;
• and
• fabricating an electrically conductive via traversing downwardly through the first region of each mounting pad, such that the electrically conductive via is located beneath the electric component when the electric component is coupled to the mounting pads.

A method of fabricating a printed circuit board, the method comprising:

• providing a first dielectric layer;
• fabricating a conductive interconnect layer on a bottom surface of the first dielectric layer, the first conductive interconnect layer having interconnect traces formed therein;
• fabricating a conductive power plane layer on a top surface of the first dielectric layer;
• fabricating a solder mask on top of the conductive power plane layer;
• and
• providing openings in the solder mask to expose the second conductive layer to increasing heat dissipation capabilities, the openings are located in the solder mask in regions which are not intended to be populated with circuit components.