Digital convergence correction device and display device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakeshi Chujo
Life of this patent
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Abstract
A problem to be solved by the invention is to provide a digital convergence correction device capable of coping with variation in scanning frequency at a reasonable price. The digital convergence correction device comprises a gate circuit for storing a variation in each convergence correction amount in a memory as correction data, and reading out the correction data synchronously with screen scanning at the time of integrating the correction data and causing the output time to be constant for each of the correction data read out.
Claims19
A digital convergence correction device, in which a convergence correction signal is generated in accordance with correction data, comprising:
- a memory for preliminarily obtaining a convergence correction amount at each convergence correction point which corresponds to a position on a screen in a relation of 1 to 1, and storing and holding a variation in each convergence correction amount with respect to an adjacent convergence correction point as correction data;
- an address counter for generating an address read out with respect to the memory synchronously with screen scanning;
- a gate circuit for controlling an output time to be constant with respect to each of the correction data read out;
- a digital/analog converter circuit for integrating the correction data from the gate circuit, and generating and outputting an analog signal;
- and
- a low-pass filter for smoothing the analog signal and generating a convergence correction signal.
A display device comprising a digital convergence correction device for generating a convergence correction signal in accordance with correction data, said digital convergence correction device comprising:
- a memory for preliminarily obtaining a convergence correction amount at each convergence correction point which corresponds to a position on a screen in a relation of 1 to 1, and storing and holding a variation in each convergence correction amount with respect to an adjacent convergence correction point as correction data;
- an address counter for generating an address read out with respect to the memory synchronously with screen scanning;
- a gate circuit for controlling an output time to be constant with respect to each of the correction data read out;
- a digital/analog converter circuit for integrating the correction data from the gate circuit, and generating and outputting an analog signal;
- and
- a low-pass filter for smoothing the analog signal and generating a convergence correction signal.
Dependencies are inferred from the claim text.