Method for forming chip scale package
AssigneeFlip Chip Technologies, L.L.C.
InventorsPeter Elenius, Harry Hollack
Life of this patent
Estimating the term…
Loading patent…
AssigneeFlip Chip Technologies, L.L.C.
InventorsPeter Elenius, Harry Hollack
Estimating the term…
A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
A method of forming a flip chip package for an integrated circuit including the steps of:
A method of forming a flip chip package for an integrated circuit, including the steps of:
Dependencies are inferred from the claim text.