US 6,286,128 B1 · Method for design optimization using logical and physical information

Method for design optimization using logical and physical information

AssigneeMonterey Design Systems, Inc.

InventorsLawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li, Robert Eugene Shortt, Christopher Dunn, David Gluss, Dennis Yamamoto, Dinesh Gaitonde, Douglas B. Boyle, Emre Tuncer, Eric McCaughrin, Feroze Peshotan Taraporevala, Gary K. Yeap, James S. Koford, Joseph T. Rahmeh, Lilly Shieh, Salil R. Raje, Sam Jung Kim, Satamurthy Pullela, Yau-Tsun Steven Li, Tong Gao

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Abstract

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Claims10

Dependent claims

A method for design optimization using logical and physical information, comprising:

receiving a behavioral description of an integrated circuit;
synthesizing, from said behavioral description, circuit elements of said integrated circuit;
and
concurrently optimizing placement and logic of said circuit elements in accordance with a cost function.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

09/097,299Filed 12 Jun 1998 · continuation in part

Priority

11 Feb 1998

Granted

4 Sep 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 2119/06
Details relating to the type or aim of the analysis or the optimisation: power analysis or power optimisation