End to end walking print
AssigneeInternational Business Machines Corporation
InventorsSamuel Neely Hopper, Christopher Starbuck Kush, John Charles Wilson
Life of this patent
Estimating the term…
Abstract
An method and apparatus for error checking. A known test pattern is written into a predetermined byte of a scan line. The method may include generating a known test pattern in a byte of a scan line and transmitting the scan line data through a first data path. The scan line data at the end of the first data path may be evaluated to determine if the test pattern is still in the predetermined byte of the scan line. If the pattern in the predetermined byte is correct, the test pattern may be removed from the predetermined byte and the scan line data may be transmitted to a print engine. If the pattern in the predetermined byte is incorrect, then a signal may be sent to terminate the transmission of the scan line data.
Claims19
A method of error checking, comprising:
- generating a known pattern in a predetermined segment of data having a plurality of segments;
- transmitting the data through a first data path having an end;
- evaluating the data at the end of the first data path to determine if the data has the known pattern;
- and
- transmitting the data through a second data path based on the evaluating of the data at the end of the first data path.
A method of error checking, comprising:
- generating a known pattern in a first byte of a first data;
- transmitting the first data from a processor to a comparator and a latch, the comparator having the known pattern;
- evaluating if the known pattern is in the first byte of the first data transmitted to the comparator;
- and
- generating a second data if the known pattern is in the first byte of the first data transmitted to the comparator.
A circuit for error checking, comprising:
- a comparator to receive a first data having a predetermined position pattern, the comparator having a known pattern, the comparator to compare the predetermined position pattern with the known pattern and generate an output;
- a latch coupled to receive the first data and generate a second data;
- and p1 a control circuit coupled to the comparator and the latch, the control circuit to signal the latch to output the second data based on the output of the comparator.
A data processing circuit, comprising:
- a processor to transmit a first data;
- a memory coupled to receive the first data from the processor;
- and
- a error checking circuit coupled to the memory and the processor, the error checking circuit comprising:
- a comparator to receive the first data having a predetermined position pattern from the memory, the comparator having a known pattern, the comparator to compare the predetermined position pattern with the known pattern and generate an output;
- a register coupled to receive the first data from the memory and generate a second data;
- and
- a control circuit coupled to the comparator, the register, and the processor, the control circuit to signal the register to output the second data based on the output of the comparator.
Dependencies are inferred from the claim text.