Semiconductor device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTokuya {overscore (O)}sawa, Hideshi Maeno
Life of this patent
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Abstract
When the RAM (10) is not initialized, data signals captured from the data output portions (do[n]) may include undefined value, but these data signals are not transferred to an MISR through the scan path (22). Transferred to the MISR are only the data signals (DI[n]) captured by the scan path (13). Accordingly, BIST can be applied to the combinational logic circuit (40) without requiring initialization of the RAM (10) and without being affected by undefined value. Thus, BIST to the combinational logic circuit (40) can be normally achieved in a short period.
Claims10
A semiconductor device comprising:
- a storage unit;
- a logic unit which exchanges data signals with said storage unit;
- a first scan path with m (≧1) stage(s) for transferring a data signal from said logic unit to said storage unit;
- a second scan path with n (≦m) stage(s) for transferring a storage data signal from said storage unit to said logic unit;
- a test pattern generating circuit for generating a test pattern and supplying the test pattern to an input end of said first scan path;
- an output data compacting circuit for outputting a signature which is a signal representing an input signal in a compacted form;
- and
- a transfer path for transferring a signal from an output end of said first scan path to said output data compacting circuit without through said second scan path;
- wherein said second scan path has an input end connected to an output of one of the first to (m−n)th stage(s) of said first scan path.
Dependencies are inferred from the claim text.