Memory architecture for automatic test equipment using vector module table
AssigneeTeradyne, Inc.
InventorsPeter A. Reichert, Benjamin J. Brown
Life of this patent
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Abstract
A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules.
Claims21
Tester system apparatus comprising:
- a) first memory means for storing a test pattern, the pattern including a data portion and a control portion, said first memory means having a plurality of address lines;
- b) a second memory having a data output and a plurality of address lines;
- c) an address counter connected to receive data from the data output of the second memory and an output coupled to the address lines of the first memory means;
- d) a second counter having an output and an input connected to receive data from the data output of the second memory;
- and
- e) control means for accessing at least one location in the second memory and loading the address counter and the second counter with data stored in the at least one location in the second memory in response to the second counter reaching a predetermined value.
A method of operating a tester comprising the steps of:
- a) loading a plurality of pattern modules into sequential access memory, each pattern module including a data and control portion;
- b) storing an ordered list of pattern modules to be executed and the location in memory of each pattern module;
- and
- c) generating addresses to the memory by:
- i) using the stored location of the first pattern module in the ordered list to generate an initial address;
- ii) advancing the address until the end of the first pattern module is reached;
- iii) repeating steps i) and ii) for successive pattern modules in the ordered list.
A method of operating a tester comprising the steps of:
- a) loading a plurality of pattern modules into nonsequential locations in a dynamic RAM memory, each pattern module comprising a plurality of vectors stored in sequential order in the memory;
- b) retrieving vectors from one of the modules in sequential order and executing the retrieved vectors at an execution rate;
- c) refreshing the dynamic RAM memory at a first refresh rate while retrieving vectors in sequential order;
- d) retrieving vectors from a second pattern module and executing the retrieved vectors at the execution rate such that vectors are executed continuously at the execution rate during a transition from the first to the second module;
- and
- e) refreshing the dynamic RAM at a second refresh rate, slower than the first refresh rate while initially retrieving vectors from the second pattern module;
- and
- f) refreshing the dynamic RAM at the first refresh rate after refreshing the dynamic RAM at the second refresh rate.
Dependencies are inferred from the claim text.