Delay fault testing with IEEE 1149.1
AssigneeNortel Networks Limited
InventorsYuejian Wu, Paul P. Soong
Life of this patent
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Abstract
An interconnect delay test uses the IEEE 1149.1 standard test access port (TAP) controller. No modification of standard boundary cells is required. Since the standard boundary scan cells are used, circuit board and/or backplane interconnect delay tests do not affect ASIC (application specific integrated circuit) designs. It allows board and system designers to add new interconnect AC tests for any signals at any time without modification of ASICs. Since the method has no impact on the operations of the standard TAP controller, it is possible to use available test softwares for interconnect DC tests to perform the proposed delay test. The method can also be integrated as part of in-system interconnect tests.
Claims46
A test access port (TAP) control method in use for delay fault test of interconnect between first and second integrated circuit (IC) chips, the method comprising the steps of:
- performing IEEE 1149.1 standard TAP operations wherein test clock (TCK), test mode select (TMS), TAP scan test clock (TAP_SCLK), TAP scan mode (TAP_SM) and TAP load (TAP_LO) signals are determined by standardized timing;
- generating a scan mode (SM) control signal in response to the TAP_SM signal;
- generating a load (LO) control signal in response to the TAP_LO signal;
- and
- generating a scan test clock (SCLK) control signal in response to the TCK signal and the LO control signal.
An apparatus for conducting delay fault test of interconnect between first and second IC chips, the apparatus comprising a test access port (TAP) controller,
- the TAP controller performing IEEE 1149.1 standard TAP operations wherein test clock (TCK), test mode select (TMS), TAP scan test clock (TAP_SCLK), TAP scan mode (TAP_SM) and TAP load (TAP_LO) signals are determined by standardized timing;
- the TAP controller generating means for generating scan mode (SM), load (LO) and scan test clock (SCLK) control signals, in response to the TAP_SM, the TAP_LO and the TCK signals.
A method for performing IEEE 1149.1 standard TAP operations, the method comprising the steps of:
- performing as defined by the IEEE 1149.1 standard, so that test clock (TCK), test mode select (TMS), TAP scan test clock (TAP_SCLK), TAP scan mode (TAP_SM) and TAP load (TAP_LO) signals are determined by standardized timing;
- generating a scan mode (SM) control signal which is activated in response to the transition of a pulse of the TAP_SM signal;
- generating a load (LO) control signal which is activated in response to the transition of a pulse of the TAP_LO signal;
- and
- generating a scan test clock (SCLK) control signal which is activated in response to the transition of a pulse of the activated LO control signal.
Dependencies are inferred from the claim text.