Scan path circuitry including a programmable delay circuit
AssigneeCypress Semiconductor Corporation
InventorsJonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy
Life of this patent
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Abstract
A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.
Claims20
A circuit for delaying a signal comprising:
- a scan register having a scan bit;
- a logic circuit coupled to the scan register and decoding the scan bit;
- and
- a programmable delay circuit coupled to the logic circuit and delaying the signal a programmable amount of time in response to the decoded scan bit.
A circuit for delaying a signal, comprising:
- means for storing a scan bit;
- means for decoding the scan bit;
- and
- means for programmably delaying the signal in response to the decode means.
A method of delaying a signal, comprising:
- decoding a scan bit in a scan register;
- and
- delaying the signal in response to decoding the scan bit.
A method of testing a device comprising the steps of:
- programming a scan bit into a scan register;
- decoding the scan bit;
- in response to the decoded scan bit, delaying a signal for a predetermined period of time;
- and
- monitoring the operation of the device in response to delaying the signal.
A circuit comprising:
- a first plurality of delay circuits each having a different delay;
- and
- a second plurality of delay circuits coupled to the first plurality of delay circuits and each having a different delay.
A circuit for delaying a signal comprising:
- a first delay circuit having an input coupled to the signal and an output;
- a second delay circuit having an input coupled to the signal and an output;
- a third delay circuit having an input coupled to the signal and an output;
- and
- a fourth delay circuit having an input coupled to each of the outputs of the second and third delay circuits, and an output coupled to the first delay circuit.
Dependencies are inferred from the claim text.