On-chip testing circuit and method for integrated circuits

An integrated circuit comprising:

• an internal bus having ‘N’ data lines;
• an embedded memory device coupled to the internal bus;
• a multiplexer having ‘N’ first data ports each coupled to a respective one of the N data lines of the internal bus and ‘M’ second data ports, where ‘M’ is less than ‘N’;
• a controller coupled to the multiplexer and selecting a subset of ‘M’ of the ‘N’ data lines in the internal bus to be coupled to the ‘M’ second data ports of the multiplexer;
• ‘M’ I/O ports each coupled to a respective one of the ‘M’ second data ports of the multiplexer;
• and
• an embedded logic array including ‘N’ data ports coupled to the ‘N’ data lines of the internal bus and a second set of ports coupled to dedicated I/O ports, the embedded logic array having been formed on the integrated circuit after functional testing of the embedded memory device.

An integrated circuit comprising:

• an embedded memory device having ‘N’ data bus terminals;
• a multiplexer having ‘N’ first data ports each coupled to a respective one of the ‘N’ data bus terminals and ‘M’ second data ports, where ‘M’ is less than ‘N’;
• and
• ‘M’ I/O ports each coupled to a respective one of the second data ports.

An integrated circuit comprising:

• an internal bus having a first data width;
• an embedded matrix memory device coupled to the internal bus;
• an embedded logic array coupled to the internal bus;
• a first set of I/O ports coupled to the embedded logic array;
• a multiplexer including a first set of data ports having the first data width coupled to the internal bus and having a second set of data ports having a second data width that is less than the first data width;
• and
• a second set of I/O ports having the second data width, the second set of I/O ports coupled to the second set of multiplexer data ports.

A computer comprising:

• a data and address bus;
• a central processing unit coupled to the data and address bus;
• an input device coupled to data and address bus;
• a display coupled to the data and address bus;
• a memory coupled to the central processing unit, the memory including a ROM storing instructions providing an operating system for the central processing unit and including a read-write memory providing temporary storage of data;
• and
• a function circuit coupled to the data and address bus, the function circuit comprising:
• an embedded memory device having ‘N’ data bus terminals;
• a multiplexer including ‘N’ first data ports each coupled to a respective one of the ‘N’ data bus terminals and including ‘M’ second data ports, where ‘M’ is less than ‘N’;
• ‘M’ I/O ports each coupled to a respective one of the ‘M’ multiplexer second data ports;
• and
• an embedded logic array including ‘N’ data ports coupled to the ‘N’ data bus terminals and also including I/O ports coupled to I/O pins.

A method of making an integrated circuit including an embedded memory device, the method comprising:

• forming the embedded memory device, redundant memory cells and a multiplexer on the integrated circuit, the multiplexer including ‘N’ data ports coupled to ‘N’ data bus terminals of the embedded memory device and ‘M’ data ports coupled to ‘M’ I/O ports, where ‘M’ is less than ‘N’;
• testing the embedded memory device by coupling test signals into and out of the embedded memory device through the multiplexer and ‘M’ I/O ports to determine if there are any defective memory cells in the embedded memory device;
• replacing defective memory cells in the embedded memory device with redundant memory cells;
• and
• forming an embedded logic array having ‘N’ data ports coupled to the ‘N’ data bus terminals of the embedded memory device, the embedded logic array including I/O ports coupled to pins of the integrated circuit.

A method of forming an embedded logic array on an integrated circuit comprising:

• coupling a group of temporary interconnections to ‘M’ I/O pads;
• coupling control signals to a multiplexer, the control signals causing the multiplexer to direct which of ‘N’ rows of an embedded memory device are coupled to the ‘M’ I/O pads, where ‘M’ is less than ‘N’;
• testing memory cells in the embedded memory device with signals coupled to the embedded memory device through the temporary interconnections and the multiplexer, and, when a memory cell fails, writing an address corresponding to the failed memory cell to a memory contained in an automated tester;
• and
• forming the embedded logic array having ‘N’ data ports coupled to the ‘N’ rows of the embedded memory device, the embedded logic array including I/O ports coupled to at least some of the I/O pads of the integrated circuit.

A method of forming an integrated circuit comprising:

• coupling a group of temporary interconnections to ‘M’ I/O pads;
• coupling control signals to a multiplexer and data compressor on the integrated circuit, the control signals directing a multiple of ‘M’ of ‘N’ rows of a memory device to couple to the ‘M’ I/O pads, where ‘M’ is less than ‘N’;
• supplying background data to the memory device through the temporary interconnections;
• extracting read data from the memory device in response to the background data;
• comparing the read data to corresponding expect data;
• and, when the read data do not agree with the corresponding expect data, writing failure data to a memory contained in an automated tester, the failure data including address information identifying a group of rows or columns of memory cells including the memory cell providing the read data that do not agree with the corresponding expect data;
• and
• forming the embedded logic array including ‘N’ data ports coupled to the ‘N’ rows of the embedded memory device, the embedded logic array including I/O ports coupled to pins of the integrated circuit.