US 6,286,092 B1 · Paged based memory address translation table update method and apparatus

Abstract

A page based memory address translation table update method and apparatus uses a first processor, such as a host processor or other processor, to notify a second processor to update its own page table. In one embodiment, the first processor generates an execution order driven page table maintenance command for the second processor. The second processor updates its own page table in sequence with received embedded commands. The second processor also updates its own translation look aside buffer in response to the page table maintenance data generated by the first processor. The page table maintenance data may be, for example, a page table maintenance command that is queued by the first processor so that the table update for the second processor is deferred from the first processors point of view since the second processor performs its own page table edits based on the order in which the page table maintenance command appears in a command queue for the second processor.

Claims24

Dependent claims

A page based memory address translation table update method for a system having a first page table associated with a first processor and a second processor, the method comprising steps including:

generating page table maintenance data by the first processor for the second processor while the second processor, is using the first page table;
and
updating, by the second processor, the first page table based on the page table maintenance data after the second processor has completed use of the first page table.

Dependencies are inferred from the claim text.

Paged based memory address translation table update method and apparatus

Life of this patent

Paged based memory address translation table update method and apparatus

Life of this patent

Abstract

Claims24