Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches

A method for selectively imposing inter-reference ordering between memory reference operations of a shared memory multiprocessor system, the system having a plurality of processors, each processor having a translation buffer (TB) configured to store a plurality of page table entries (PTEs), each PTE containing information for mapping a virtual address to a physical address of a page stored in a memory of the system, the method comprising the steps of:

• issuing a memory reference operation from a processor to control logic of the multiprocessor system to retrieve a PTE associated with a specific page in the memory;
• generating a commit-signal at the control logic in response to the issued memory reference operation, the commit-signal being generated substantially sooner than completion of the memory reference operation and indicating apparent completion of the memory reference operation rather than actual completion of the operation;
• receiving the PTE at the processor in response to the memory reference operation;
• and
• loading the received PTE into the TB only upon receipt of the commit-signal associated with the memory reference operation at the processor.