Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsJoo Sun Choi, Seok Cheol Yoon
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Abstract
A chip set memory controller having a data strobe mask function is disclosed. The controller includes first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, whereby the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, for thereby implementing a reverse compatibility of a DQM function by additionally installing a pin in a DDR SDRAM and masking a data strobe signal.
Claims10
A synchronous semiconductor memory device with a plurality of memory modules, the memory modules operating in synchronous with a clock signal, comprising:
- a chip set memory controller that controls a data input/output of the plurality of memory modules by outputting the clock signal;
- and
- a data strobe mask signal pin for receiving a data strobe mask signal,
- wherein in reading a data from the plurality of memory modules, the plurality of memory modules provides the chip set memory controller with a data strobe signal for strobing the data, and the chip set memory controller outputs a data mask signal for masking the data and an additional data strobe mask signal for masking the data strobe signal, to the plurality of memory modules.
A synchronous semiconductor memory device comprising:
- a chip set memory controller having a data strobe mask function,
- first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, and
- a data strobe mask signal pin for receiving a data strobe mask signal,
- whereby the data inputted into each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data inputted into each memory module is controlled by a data strobe signal outputted from each memory module.
A synchronous semiconductor memory device, comprising:
- first to N-th memory modules having a plurality of memory devices, and,
- a chip set memory controller for controlling the operations of the first to N-th memory modules, the chip set memory controller having a data strobe mask function,
- wherein the first through N-th memory modules operate in synchronous with a clock signal outputted from the chip set memory controller, wherein the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, wherein the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, wherein the chip set memory controller outputs a data strobe mask signal controlling the operation of the data strobe signal, and wherein each of the memory devices include a data strobe mask signal pin for receiving the data strobe mask signal;
- and
- wherein said each memory module includes a plurality of DDR SDRAMs.
Dependencies are inferred from the claim text.