High speed memory-based buffer and system and method for use thereof

A buffer configured to store a plurality of data entries, the buffer comprising:

• a memory including a plurality of data entry storage locations;
• a plurality of clocked storage elements each configured to store one of the plurality of data entries, wherein the plurality of clocked storage elements are coupled between an output of the memory and an output of the buffer, wherein the plurality of clocked storage elements include a first clocked storage element and a second clocked storage element, wherein each of the first clocked storage element and the second clocked storage element are coupled to receive the output of the memory, and wherein the first clocked storage element is coupled to receive the output of the second clocked storage element;
• and
• control logic coupled to the one or more clocked storage elements and to the memory.

A method of buffering data through a buffer storing a plurality of data entries, the buffer including a memory having a plurality of data entry storage locations and one or more registers chained from the output of the memory, each register configured to store one of the plurality of data entries, wherein the one or more registers includes an intermediate register coupled between said memory and an output register, the method comprising:

• reading a first data entry out of the memory and into said output register of the one or more registers;
• the buffer receiving a read request;
• providing said first data entry from said output register in response to the buffer receiving said read request;
• reading a second data entry out of the memory and into said output register in response to said providing said first data entry from said output register;
• and
• reading a third data entry out of the memory and into said intermediate register after said reading said second data entry out of the memory and into said output register.

A method of buffering data through a buffer storing a plurality of data entries, the buffer including a memory having a plurality of data entry storage locations and one or more registers chained from the output of the memory, each register configured to store one of the plurality of data entries, wherein the one or more registers includes an intermediate register coupled between said memory and an output register, wherein an input to the buffer is coupled to an input to the intermediate register, the method comprising:

• reading a first data entry out of the memory and into said output register of the one or more registers;
• the buffer receiving a read request;
• providing said first data entry from said output register in response to the buffer receiving said read request;
• the buffer receiving a write request;
• and
• writing a second data entry into said intermediate register in response to the buffer receiving the write request.

A system for buffering data, the system comprising:

• means for storing a plurality of data entries;
• a plurality of means for storing single data entries, wherein the plurality of means for storing single data entries are chained from the output of the means for storing the plurality of data entries, the plurality of means for storing single data entries includes a first means and a second means, wherein the output of the means for storing a plurality of data entries is coupled to the inputs of the first means and the second means, wherein the output of the second means is coupled to the input to the first means;
• means for reading a first data entry out of the means for storing the plurality of data entries and into an output one of the plurality of means for storing single data entries;
• means for receiving a read request;
• and
• means for providing the first data entry from the output one of the plurality of means for storing single data entries in response to the means for receiving the read request receiving the read request.

A system for routing data between data ports, comprising:

• one or more output ports coupled to receive data from a plurality of input ports;
• a plurality of buffers coupled to the plurality of input ports, wherein each of the plurality of buffers are configured to accept data from a respective input port, wherein each of said plurality of buffers comprises:
• a memory including a plurality of data entry storage locations;
• a plurality of registers each coupled to store one of a plurality of data entries, wherein the plurality of registers are coupled between an output of the memory and an output of the buffer, wherein the plurality of registers include a first register and a second register, wherein the inputs of the first register and the second register are coupled to receive the output of the memory, wherein the input to the first register is coupled to receive the output of the second register;
• and
• control logic coupled to the plurality of registers and to the memory, wherein the control logic is configured to control the operations of the buffer, wherein the control logic is configured to output an empty control signal when said buffer is empty of data entries;
• a plurality of input multiplexers coupled to the plurality of input ports, wherein each of the plurality of input multiplexers is further coupled to receive an output of a respective one of the plurality of buffers, wherein said empty control signal from the respective one of the buffers selects between data from the respective input port and the respective buffer;
• and
• one or more output multiplexers coupled to receive data from the plurality of input multiplexers, wherein each of the one or more output multiplexers is configured to provide output data to a respective one of the one or more output ports.