System and method for synchronizing data communication between asynchronous buses
AssigneeInternational Business Machines Corporation
InventorsFrancis Bredin, Claude Sitbon
Life of this patent
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Abstract
A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. The synchronization circuit is responsive to a control signal generated by memory status means coupled to a memory which temporarily stores data transmitted from the emitter bus to the receiver bus. The control signal representative of the status of the memory is reflecting asynchronous read and write operations within the memory. The resultant signal output from the synchronization circuit is a one clock synchronized signal such that rising and falling transitions are synchronized to the receiver bus clock frequency.
Claims9
A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency said bridge comprising:
- a memory for temporarily storing data transmitted from the emitter bus to the receiver bus;
- a memory status coupled to the memory for generating a control signal (MEMSTAT) indicating the status of said memory;
- and
- a synchronization circuit responsive to said control signal (MEMSTAT) for generating a synchronized signal (SF) such that rising and falling transitions of the synchronized signal (SF) are synchronized to the receiver clock frequency said synchronization circuit comprising:
- a Negative Edge Detector (NED) responsive to falling transitions of said control signal (MEMSTAT) for generating a first enabling signal;
- a Positive Edge Detector (PED) responsive to rising transitions of said control signal (MEMSTAT) for generating a second enabling signal, whereby the NED and PED are cross-coupled with the first enabling signal operates as an enabling input to the PED and the second enabling signal operates as an enabling input to the NED;
- a clock latch responsive to the first enabling signal and to the receiver bus clock for generating a clocked signal, whereby the clocked signal operates as a restore input to the PED;
- and
- an output circuit responsive to said clocked signal and said second enabling signal for generating said synchronized signal (SF).
Dependencies are inferred from the claim text.