Shared memory access device and method
AssigneeFujitsu Limited
InventorKunihiro Ohara
Life of this patent
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Abstract
A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority than the other microcontroller(s). In the case of competing requests, while one microcontroller is granted access to the memory, the other microcontroller performs other processing, and polls a memory status register to determine when the memory is available. Since the waiting processor performs other operations, as opposed to idling, the efficiency of the microcontroller is improved.
Claims8
A method for arbitrating access requests to a shared memory from a plurality of controllers including a first controller and a second controller having a lower access priority than the first controller, the method comprising:
- setting an operation mode of the second controller in one of a wait mode and a non-wait mode;
- deciding the access enabling of the first controller and deciding the access disabling of the second controller in accordance with an access priority when a first access request and a second access request from the first and second controllers compete with each other;
- and
- supplying a first signal for resetting a wait state for the first controller;
- and
- supplying a second signal for resetting a wait state for the second controller such that the second controller executes other processing when the second controller is set in the non-wait mode and the access to the shared memory by the second controller is disabled.
A bus controller for arbitrating access requests to a shared memory from a plurality of controllers including a first controller and a second controller having a lower access priority than the first controller, the bus controller comprising:
- a first register for storing one of wait mode data and non-wait mode data set for the second controller;
- an arbitration circuit, connected to the first and second controllers for receiving access requests from the first and second controllers, and for deciding the access enabling of the first controller and deciding the access disabling of the second controller when the access requests from the first and second controllers compete with each other;
- a first bus access controller, connected to the arbitration circuit, for supplying a first signal for resetting the wait state of the first controller in accordance with the decision of the access enabling of the first controller;
- and
- a second bus access controller, connected to the first register and the arbitration circuit, for supplying a second signal for resetting the wait state of the second controller when the access disabling of the second controller is determined and the non-wait mode data is stored in the first register.
An electronic device, comprising:
- a plurality of controllers including first and second controllers;
- a memory shared by the plurality of controllers, wherein the second controller has a lower access priority than the first controller;
- and
- a bus controller, connected between the plurality of controllers and the memory, for arbitrating access requests to the shared memory from the plurality of controllers, the bus controller including,
- a first register for storing one of wait mode data and non-wait mode data set for the second controller,
- an arbitration circuit, connected to the plurality of controllers for receiving access requests from the first and second controllers, and for deciding the access enabling of the first controller and access disabling of the second controller when the access requests from the first and second controllers compete with each other,
- a first bus access controller, connected to the arbitration circuit, for supplying a first signal for resetting a wait state of the first controller in accordance with the decision of the access enabling of the first controller, and
- a second bus access controller, connected to the first register and the arbitration circuit, for supplying a second signal for resetting the wait state of the second controller when the access disabling to the second controller is determined and the non-wait mode data is stored in the first register.
Dependencies are inferred from the claim text.