Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus
AssigneeMicron Technology, Inc.
InventorKevin J. Ryan
Life of this patent
Estimating the term…
Abstract
A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to achieve wide data paths and to support a high number of memory devices, such as dynamic random access memory devices, per data bus. The packet protocol is defined to compensate for the delay stages of the pipelined memory subsystem in order to optimize the access time of the memory devices.
Claims28
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;
- a plurality of M memory devices wherein each memory device internally contains a data in and a data out buffer and contains a column decoder and a row decoder;
- a command buffer connected between the command and address bus and the plurality of memory devices, the command buffer receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices, wherein the command buffer is shared by the plurality of M memory devices;
- and
- a data buffer connected between the plurality of M memory devices and the bidirectional data bus, the data buffer receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of M memory devices for a write operation, the data buffer receiving and latching the data information from the plurality of M memory devices and driving the data information to the bidirectional data bus for a read operation, wherein the data buffer is shared by the plurality of M memory devices.
A method for storing data in a pipelined memory system having a plurality of memory devices, wherein each memory device includes addressable storage, a data in buffer, a data out buffer, a column decoder and a row decoder, the method comprising:
- communicating commands and addresses to a unidirectional command and address bus;
- communicating data to a bidirectional data bus;
- latching the commands and addresses in a plurality of command buffers buffer, wherein each of the plurality of command buffers is shared by M of the plurality of memory devices and is positioned between the command and address bus and the plurality of memory devices;
- latching the data in a plurality of data buffers, wherein each of the plurality of data buffers is shared by the M memory devices;
- driving the latched commands and addresses to the column and row decoders of the plurality of memory devices;
- driving the latched data to the data in buffers of the plurality of memory devices;
- and
- storing the data in the addressable storage of one of the plurality of memory devices.
A method of reading data from a memory device in a pipelined memory system, comprising:
- communicating commands and addresses on a unidirectional command and address bus;
- latching the commands and addresses in a plurality of command buffers, wherein each of the plurality of command buffers corresponds to M of a plurality of memory devices and is positioned between the command and address bus and the plurality of M memory devices;
- driving the latched commands and addresses to the plurality of memory devices, wherein each of the plurality of memory devices includes addressable storage, a data in buffer, a data out buffer, a column decoder and a row decoder;
- communicating data from the addressable storage of one of the plurality of memory devices;
- latching the data in a data buffer, wherein the data buffer is shared by a plurality of memory devices;
- and
- receiving the data on a bidirectional data bus.
An electronic system comprising:
- a microprocessor;
- a memory controller coupled to the microprocessor;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data to the bidirectional data bus for a write operation and receiving the data from the bidirectional data bus during a read operation;
- a plurality of M memory devices wherein each memory device contains a data in and a data out buffer, a column and a row decoder;
- a command buffer connected between the command and address bus and the plurality of memory devices, the command buffer receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices, wherein the command buffer is shared by the plurality of M memory devices;
- and
- a data buffer connected between the plurality of memory devices and the bidirectional data bus, the data buffer receiving and latching the data from the bidirectional data bus and driving the data to the plurality of memory devices for a write operation, the data buffer receiving and latching the data from the plurality of memory devices and driving the data to the bidirectional data bus for a read operation, wherein the data buffer is shared by the plurality of M memory devices.
In an electronic system having a memory controller and a plurality of memory subsystems, including a first memory subsystem, wherein each memory subsystem includes a command buffer, a data buffer and a plurality of memory devices, wherein each memory device includes a data in and a data out buffer, a column decoder and a row decoder, a method of processing information within the electronic system, comprising:
- communicating information to the memory controller;
- communicating commands and addresses on a unidirectional command and address bus;
- communicating data on a bidirectional data bus;
- latching the commands and addresses received from the unidirectional command and address bus in the command buffer of the first memory subsystem, wherein the command buffer is shared by the plurality of memory devices and is positioned between the command and address bus and the plurality of memory devices;
- receiving and latching the data in the data buffer of the first memory subsystem, wherein the data buffer is shared by the plurality of memory devices;
- driving the latched commands and addresses to the plurality of memory devices of the first memory subsystem;
- driving the latched data to the plurality of memory devices of the first memory subsystem for a write operation;
- and
- driving the data to the bidirectional data bus for a read operation.
In an electronic system having a memory controller and a plurality of memory subsystems, including a first memory subsystem, wherein each memory subsystem includes a command buffer and a data buffer shared by a plurality of memory devices, wherein each memory device includes a data in and a data out buffer, a column decoder and a row decoder, a method of storing data in one of the plurality of memory devices, comprising:
- communicating information to the memory controller;
- communicating commands and addresses on a unidirectional command and address bus;
- communicating data on a bidirectional data bus;
- latching the commands and addresses read from the unidirectional command and address bus in the command buffer of the first memory subsystem, wherein the command buffer is positioned between the command and address bus and the plurality of memory devices;
- latching the data received from the bidirectional data bus in the data buffer of the first memory subsystem;
- driving the latched commands and addresses to the plurality of memory devices of the first memory subsystem;
- driving the latched data to the plurality of memory devices of the first memory subsystem;
- and
- storing the data in addressable storage of one of the plurality of memory devices of the first memory subsystem.
In an electronic system having a memory controller and a plurality of memory subsystems, including a first memory subsystem, wherein each memory subsystem includes a command buffer and a data buffer shared by a plurality of memory devices, wherein each memory device includes a data in and a data out buffer, a column decoder and a row decoder, a method of reading data from one of the plurality of memory devices, comprising:
- communicating information to the memory controller;
- communicating commands and addresses on a unidirectional command and address bus;
- latching the commands and addresses read from the unidirectional command and address bus in the command buffer of the first memory subsystem wherein the command buffer is positioned between the command and address bus and the plurality of memory devices;
- driving the latched commands and addresses to the plurality of memory devices of the first memory subsystem;
- communicating data from addressable storage of one of the plurality of memory devices of the first memory subsystem;
- latching the data in the data buffer of one of the plurality of the first memory subsystem;
- and
- receiving the data on the bidirectional data bus.
Dependencies are inferred from the claim text.