Signal processor delta-sigma modulator stage
AssigneesSony Corporation, Sony United Kingdom Limited
InventorsPeter Charles Eastty, Christopher Sleight, Peter Damien Thorpe, James Andrew Scott Angus
Life of this patent
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Abstract
A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.
Claims8
A signal processor comprising
- a series arrangement of 1-bit nth order (where n is one or more) Delta-Sigma Modulator stages with inter stage filtering, each stage having an input for receiving a 1-bit signal;
- an output for outputting a processed 1-bit signal;
- a linear signal processing section which produces a p bit signal in response to the input 1-bit signal;
- a filter section providing a desired inter stage filter characteristic and operating on said p bit signal;
- a noise shaping section for shaping a signal corresponding to a processed 1 bit signal such that noise is minimized and feeding back the shaped signal to a summer at the output of the filter section for summing the shaped signal with the filtered signal;
- and
- a quantizer which converts the summed signal to the processed 1-bit signal at said output.
A 1-bit nth order (where n is one or more) Delta-Sigma Modulator stage for use in a signal processor having a plurality of Delta-Sigma Modulator stages in cascade, the stage comprising:
- an input for receiving a 1-bit signal;
- an output for outputting a processed 1-bit signal;
- a linear signal processing section which produces a p bit signal in response to the input 1-bit signal;
- a filter section providing a desired inter stage filter characteristic and operating on said p bit signal;
- a noise shaping section for shaping a signal corresponding to a processed 1-bit signal such that noise is minimized and feeding back the shaped signal to a summer at the output of the filter section for summing the shaped signal with the filtered signal;
- and
- a quantizer which converts the summed signal to the processed 1-bit signal at said output.
A 1-bit nth order (where n is one or more) Delta-Sigma Modulator stage comprising:
- an input for receiving a 1-bit signal;
- an output for outputting a processed 1-bit signal;
- a linear signal processing section which produces a p bit signal in response to the input 1-bit signal;
- a filter section providing a desired filter characteristic and operating on said p bit signal;
- a noise shaping section for shaping a signal corresponding to a processed 1-bit signal such that noise is minimized and feeding back the shaped signal to a summer at the output of the filter section for summing with the filtered signal;
- and
- a quantizer which converts the summed signal to the processed 1-bit signal at said output.
Dependencies are inferred from the claim text.