US 6,285,975 B1 · System and method for detecting floating nodes within a simulated integrated circuit

Abstract

A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit. The two resistors operate in combination to pull the input node to a voltage level near the midpoint between the higher and lower potentials. This midpoint voltage level turns on transistors having control terminals coupled to the input node and may consequently produces a relatively large current between the power supply and ground. This large current is easily detectable from the simulation output and may be used to locate which, if any, gates may have floating inputs that cause large static currents.

Claims21

Dependent claims

A computer software program embodied on a computer readable medium, wherein the computer software program comprises a plurality of instructions configured to detect floating nodes in an integrated circuit, when executed, the computer software program performing steps comprising of:

selecting a plurality of potentially floating nodes from a data file representing the integrated circuit;
simulating a first set of one or more resistors coupling each of the plurality of potentially floating nodes to a high voltage;
simulating a second set of one or more resistors coupling each of the plurality of potentially floating nodes to a low voltage, wherein the combination of the first and second sets of resistors are configured to cause floating nodes within the plurality of potentially floating nodes to reach a predetermined intermediate voltage level between the low voltage level and the high voltage level without materially influencing the voltage levels of non-floating nodes within the plurality of potentially floating nodes;
causing the circuit to enter a simulated test state;
and
measuring the simulated static current flowing through the circuit.

3 more elements

Dependencies are inferred from the claim text.

System and method for detecting floating nodes within a simulated integrated circuit

Life of this patent

System and method for detecting floating nodes within a simulated integrated circuit

Life of this patent

Abstract

Claims21