Verification method by means of comparing internal state traces

A method for chip verification by comparing internal state traces of chips, in a chip design stage, comprising the steps of:

• a) performing an application program for each of a target system having a target chip and a system having a function verification chip model of a design stage, using a virtual system modeled by a hardware description language;
• b) storing an internal state of said target chip on a command-by-command basis during execution of said application program and generating a trace file;
• c) comparing the internal state of the target chip stored in said trace file with an internal state of the function verification chip model on a command-by-command basis;
• d) continuing execution of the said application program if the respective internal states compared in step c) are the same;
• and
• e) outputting the internal state and ending execution if the respective internal states compared in step c) are different,
• wherein an overall internal state of said target chip is stored initially, and after that, only a state difference between the internal states after and execution of a previous command and after completion of a current commend is stored, thereby reducing a size of said trace file.