Variable length code decoder for MPEG
AssigneeHyundai Electronics Industries Co., Ltd.
InventorYoung Goan Kim
Life of this patent
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Abstract
A variable length code decoder for MPEG (Motion Picture Expert Group) includes a barrel shifter for outputting the bit stream being decoded, a register for storing the output data of the barrel shifter, a finite state machine for parsing the output data of the barrel shifter and determining whether the data is an ordinary data or a more than 16-bit data, and outputs resultant control signals, a multiplexer for selectively outputting the output data of the barrel shifter or the register based on the control signal, and a decoding units for decoding a variable length code, a header code of a MPEG2 syntax from the output of the multiplexer in accordance with the control signal of the finite state machine. The variable length code decoder obtains a data throughput rate equivalent to the using of 32-bit data path.
Claims14
A variable length code decoder for MPEG (Motion Picture Expert Group), comprising:
- a barrel shifter for outputting the bit stream being decoded;
- a register for storing the output data of the barrel shifter;
- a finite state machine for parsing the output data of the barrel shifter and determining whether the data is ordinary data or more than 16-bit data, and outputs resultant control signals;
- a multiplexer coupled to receive inputs from the barrel shifter and the register and the control signal from the finite state machine for selectively outputting the output data of one of the barrel shifter and the register based on the number of bits of data;
- and
- a decoding unit for decoding a variable length code, a header code of a MPEG2 syntax from the output of the multiplexer in accordance with the control signal of the finite state machine.
A decoder circuit for video data, comprising:
- a first register, to output a coded bit stream;
- a second register, to store the output data of the first register;
- a finite state machine, which receives the output data of the first register, determines a data type from between a first type of 16 bits or fewer and a second type of greater than 16 bits, and outputs at least one control signal in accordance with the type of data;
- a multiplexer coupled to receive the output of each of the first and second registers, and to selectively output data outputted from one of the first and second registers according to the the type of data;
- and
- a decoder coupled to receive and decode the output of the multiplexer according to the control signal.
Dependencies are inferred from the claim text.