10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports

A clock recovery circuit comprising

• a first phase comparator that detects a phase difference between a reference clock signal and a first input data signal, wherein the first phase comparator outputs a first lead pulse when the reference clock signal leads the first input data signal and outputs a first lag pulse when the reference clock signal lags the first input data signal;
• a second phase comparator that detects a phase difference between the reference clock signal and a second input data signal, wherein the second phase comparator outputs a second lead pulse when the reference clock signal leads the second input data signal and outputs a second lag pulse when the reference clock signal lags the second input data signal;
• a first pulse generator that responds to first lead pulses and to first lag pulses by providing a first pumpup/pumpdown output signal that includes pumpup pulses that correspond to each first lead pulse and pumpdown pulses that correspond to each first lag pulse;
• a second pulse generator that responds to second lead pulses and to second lag pulses by providing a second pumpup/pumpdown output signal that includes pumpup pulses that correspond to each second lead pulse and pumpdown pulses that correspond to each second lag pulse;
• a first pulse combiner that logically ORs the first pumpup/pumpdown output signal and the second pumpup/pumpdown output signal to provide a combined pumpup/pumpdown output signal;
• a first pulse stream attenuator that masks out every N pulses from the combined pumpup/pumpdown output signal to provide a proportional control attenuator pulse signal, where N is an integer that provides a predefined amount of proportional control;
• a second pulse stream attenuator that masks out every M pulses from the combined pumpup/pumpdown output signal to provide an integral control attenuator pulse signal, where M is an integer that provides a predefined amount of integral control;
• an integrator that integrates the integral control attenuation pulse signal to provide an integrated up/down pulse signal;
• and
• a second pulse combiner that combines the proportional control attenuation pulse signal and the integrated up/down pulse signal to provide an up/down output pulse stream having a pulse density proportional to the phase error and attenuated by proportional gain and by past history of the phase error.