Address transition detector architecture for a high density flash memory device
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsKazuhiro Kurihara, Thomas T. Shieh
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Abstract
An equalization circuit for an address transition detector of a high density flash memory device is disclosed. The equalization circuit substantially equalizes the electrical characteristics of a particular signal path to those of another signal path wherein these signal paths transmit trigger signals which further generate other signals. The equalization ensures that resultant signals generated from the trigger signals which traverse these signal paths are generated in the same manner and with the same timing no matter which signal path the trigger signal travels down.
Claims12
An address transition detector for a high density flash memory device, said flash memory device comprising a plurality of inputs and an array of single level flash memory cells, said address transition detector comprising:
- first one or more signal transition detectors coupled with a first one or more of said plurality of inputs through a first one or more signal paths, each of said first one or more signal transition detectors operative to detect when a corresponding of said first one or more of said plurality of input signals transition and generate a first transition detect signal;
- second one or more signal transition detectors coupled with a second one or more of said plurality of inputs through a second one or more signal paths, each of said second one or more signal transition detectors operative to detect when a corresponding of said second one or more of said plurality of input signals transition and generate a second transition detect signal;
- a transition signal path coupled with said first one or more signal transition detectors and operative to transmit said first transition detect signal;
- an equalization circuit coupled with said second one or more signal transition detectors and operative to transmit said second transition detect signal;
- an address transition detect pulse generator coupled with said transition signal path and said equalization circuit and operative to receive said first and second transition detect signals and generate an address transition detect pulse wherein said address transition detector is located closer to said second one or more of said plurality of inputs than said first one or more of said plurality of inputs;
- and
- wherein said first one or more signal paths are characterized by a first delay and said equalization circuit is characterized by a second delay wherein said first delay is substantially equivalent to said second delay.
An equalization circuit for equalizing the generation of an address transition detect signal for a high density flash memory device comprising an array of single level flash memory cells, said equalization circuit comprising:
- a first receiver for receiving a first signal transition from a first signal input over a first signal path characterized by a first delay;
- a second receiver for receiving a second signal transition from a second signal input over a second signal path characterized by a second delay, wherein said second delay is shorter than said first delay;
- an equalizer coupled with said second receiver and operative to substantially equalize said first delay to said second delay.
A method of synchronizing the generation of an address transition detect signal for a high density flash memory device comprising an array of single level flash memory cells, said method comprising:
- transmitting a first signal over a first signal pith characterized by a first delay;
- transmitting a second signal over a second signal path characterized by a second delay, said second delay being less than said first delay;
- and
- equalizing said second delay and said first delay such that said first delay is substantially equivalent to said second delay.
Dependencies are inferred from the claim text.