High-speed clock circuit for semiconductor memory device
AssigneeTexas Instruments Incorporated
InventorWilbur C. Vogley
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Abstract
A synchronous dynamic random access memory (SDRAM) (500) is disclosed. The SDRAM (500) operates in synchronism with differential clock signals (CLK and /CLK). A timing and control circuit (510) compares the complementary differential clock signals (CLK and /CLK) to generate an internal clock signal (CLKI). By comparing the differential clock signals (CLK and /CLK) to generate the internal clock signal (CLKI), the preferred embodiment can compensate for degradations in the differential clock signals (CLK and /CLK). In addition, by utilizing the internal timing signal (CLKI) the preferred embodiment does not have to employ more complex circuits that must operate in synchronism with the edges of both differential clock signals (CLK and /CLK).
Claims18
A semiconductor memory device, comprising:
- an array of memory cells including a plurality of memory cells disposed in rows and columns;
- a column select circuit coupled between the array of memory cells and a plurality of data input/outputs (I/Os), the column select circuit providing access to selected columns of the array of memory cells by way of the I/Os, the column select circuit being enabled in synchronism with a single internal control clock signal;
- and
- a clock circuit that receives a first differential system clock signal and a second differential system clock signal that is complementary to the first clock signal, and generates the single internal control clock signal, the single internal control clock signal having a first logic value when the first differential system clock signal is greater than the second differential system clock signal, and a second logic value when the first differential system clock signal is less than the second differential system clock signal, wherein the single internal control clock signal substantially compensates for any degradation in the first and second differential system clock signals.
A random access memory (RAM) having a plurality of memory cells, comprising:
- a first clock node that receives a first differential system clock signal that varies between a first logic value and a second logic value;
- a second clock node that receives a second differential system clock signal that is generally the inverse of the first clock signal;
- and
- a comparator circuit having a first input coupled to the first clock node, a second input coupled to the second clock node, and an output node, the comparator circuit driving the output node to a first logic level when the first input is less than the second input and to a second logic level when the second input is less than the first input, the signal at the output node controlling the access to memory cells of the RAM, wherein the signal at the output node substantially compensates for any degradation in the first and second differential system clock signals.
A method for operating a synchronous memory device that receives differential clock signals at a first frequency, the method comprising the steps of:
- receiving the differential clock signals;
- comparing the differential clock signals to one another;
- generating a single internal clock signal at the first frequency based upon the comparison between the differential clock signals, wherein the single internal clock signal substantially compensates for any degradation in the differential clock signals;
- and
- accessing memory cells within the synchronous memory device according to the single internal clock signal.
Dependencies are inferred from the claim text.