Multilevel memory access method
OwnerHan-Ping Cheninventor
Life of this patent
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Abstract
A method and apparatus provides multi-level memory data input-output signals to speed up the memory data transfer rate between a memory controlling device and a memory device to increase the utilization of the data width of the memory cell array. Also, the present invention provides a method that is compatible with the structure of existing memory chips and modules.
Claims19
A memory access control system comprising:
- (a) a memory system controller;
- (b) a plurality of memory system address-control lines;
- (c) a plurality of binary memory system data lines;
- (d) a plurality of multilevel memory system data lines;
- (e) a plurality of first multilevel-to-binary data signal converters;
- (f) a plurality of memory devices, each having a plurality of memory device address-control lines, a plurality of binary memory device data lines, a plurality of binary memory cells, and a plurality of first binary-to-multilevel data signal converters;
- wherein the memory controller generates memory address-control signals on the memory system address-control lines;
- wherein memory address-control signals on the memory device address-control lines are derived, at least in part, from the memory system address-control lines.
- wherein memory data from memory cells are selected by the memory device address-control lines and placed on the binary memory device data lines;
- wherein said first binary-to-multilevel data signal converters transform data signals from the binary memory device data lines to the multilevel memory system data lines;
- wherein said first multilevel-to-binary data signal converters transform data signals from the multilevel memory system data lines to the binary memory system data lines.
A memory chip or module unit comprising:
- (a) a plurality of memory unit address-control lines;
- (b) a plurality of binary memory unit data lines;
- (c) a plurality of multilevel memory unit data lines;
- (d) a plurality of first multilevel-to-binary data signal converters;
- (e) a plurality of memory sub-units each having a plurality of memory sub-unit address-control lines, a plurality of binary memory sub-unit data lines, a plurality of binary memory cells, and a plurality of first binary-to-multilevel data signal converters;
- wherein memory address-control signals on the memory sub-unit address-control lines are derived, at least in part, from the memory unit address-control lines;
- wherein memory data from memory cells are selected by the memory sub-unit address-control lines and placed on the binary memory sub-unit data lines;
- wherein said first binary-to-multilevel data signal converters transform data signals from the binary memory sub-unit data lines to the multilevel memory unit data lines;
- wherein said first multilevel-to-binary data signal converters transform data signals from the multilevel memory unit data lines to the binary memory unit data lines.
In combination with a memory control system having a memory system address-control bus, a binary memory system data bus, a multilevel memory system data bus, a signal converter that transforms data signals from the multilevel memory system data bus to the binary memory system data bus, and a memory access controller which generates memory system address-control signals to access memory data through the multilevel memory system data bus, a semiconductor memory device, chip, or module unit comprising:
- (a) a plurality of memory unit address-control lines;
- (b) a plurality of multilevel memory unit data lines;
- (c) a plurality of binary-to-multilevel data signal converters;
- (d) a plurality of memory sub-units each having a plurality of memory sub-unit address-control lines, a plurality of binary memory sub-unit data lines, and a plurality of binary memory cells;
- wherein memory address-control signals on the memory sub-unit address-control lines are derived, at least in part, from the memory unit address-control lines;
- wherein memory data from memory cells are selected by the memory sub-unit address-control lines and placed on the binary memory sub-unit data lines;
- wherein the binary-to-multilevel data signal converters transform data signals from the binary memory sub-unit data lines to the multilevel memory unit data lines.
Dependencies are inferred from the claim text.