Device and method for repairing a memory array by storing each bit in multiple memory cells in the array

A memory system comprising:

• a memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of alternating even and odd word lines;
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of alternating even and odd word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• address buffers for receiving memory address and outputting corresponding row and column address;
• row decoder circuitry coupled to the memory array and the address buffers for energizing at least two word lines in the memory array in accordance with each corresponding row address, the row decoder circuitry comprising:
• refresh enable circuitry configurable to output an even row decoder enabling signal and an odd row decoder enabling signal;
• an even row decoder coupled to the refresh enable circuitry, the memory array, and the address buffers, and enable in response to the even row decoder enabling signal to energize one or more even word lines in the memory array in accordance with each corresponding row address;
• and
• an odd row decoder coupled to the refresh enable, circuitry, the memory array, and the address buffers and enable in response to the odd row decoder enabling signal to energize one or more odd word lines in the memory array in accordance with each corresponding row address;
• a column decoder coupled to the address buffers for outputting corresponding row and column addresses;
• sense amplifier and input/output gating circuitry coupled to the column decoder and the memory array for selecting a pair of the plurality of pairs of complementary digit lines in the memory array in accordance with each column select signal in order to access two or more memory cells in the memory array each coupled to one of the selected digit lines of the plurality of pairs of complementary digit lines and one of the at least two energized word lines;
• and
• a data buffer coupled to the sense amplifier and input/output gating circuitry for communication between the accessed memory cells and external circuitry.

A memory system comprising:

• a memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of odd word lines;
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of odd word lines and an access terminal coupled to one of the plurality of pairs of complimentary digit lines;
• address buffers for receiving multiplexed memory addresses in the form of a first plurality of address bits followed in time by a second plurality of address bits, for outputting a row address and a first portion of a column address for each multiplexed memory address corresponding to the first plurality of address bits associated with the multiplexed memory address, and for outputting a second portion of the column address for each multiplexed memory address corresponding to the second plurality of address bits associated with the multiplexed memory address;
• row decoder circuitry coupled to the memory array and the address buffers energizing at least two word lines in the memory array in accordance with each row address;
• a column decoder coupled to the address buffers outputting a column select signal in accordance with the first and second portions of each column address;
• sense amplifier and input/output gating circuitry coupled to the column decoder and the memory array selecting a pair of complementary digit lines of the plurality of pairs of complimentary digit lines in the memory array in accordance with each column select signal accessing at least two memory cells in the array, each memory cell coupled to one of the selected digit lines of the plurality of pairs of complementary digit lines and one of the at least two energized word lines;
• and
• a data buffer coupled to the sense amplifier and input/output gating circuitry communicating between the accessed memory cells and external circuitry.

An apparatus used with a memory array including a plurality of pairs of complementary digit lines through which a plurality of memory cells activated by a plurality of word lines selected in accordance with addresses may be accessed, the apparatus comprising:

• a memory array including:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells, each memory cell of the plurality of memory cells having a control terminal coupled to one word lines of a pair of the plurality of word lines and an access terminal coupled to one digit lines of a pair of the plurality of pairs of complementary digit lines;
• enabling circuitry enabling use of the apparatus with the memory array;
• and
• energizing circuitry coupled to the enabling circuitry to energize at least two of the word lines of the plurality of word lines in the memory array in accordance with a first row address in response to the enabling circuitry enabling using the apparatus with the memory array so at least two of the plurality of memory cells accessible through one pair of complementary digit lines of the plurality of pairs of complementary digit lines may be accessed for the first row address and for energizing at least four of the word lines of the plurality of word lines in the memory array in accordance with a second row address in response to the enabling circuitry enabling use of the apparatus with the memory array so said at least four of the plurality of memory cells accessible through one the pairs of complementary digit lines of the plurality of word lines may be accessed for the second row address.

A memory apparatus comporising:

• a memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling effecting refreshing of the memory array;
• and
• word line energizing circuitry coupled to the memory array and the enabling circuitry for energizing more than one of the plurality of word lines in the memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of the memory array so two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

An integrated circuit memory device comprising:

• a memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the of the plurality word lines and an access terminal coupled to one of the of the plurality of pairs of complementary digit lines;
• enabling circuitry for effecting refreshing of the memory array;
• and
• word line energizing circuitry coupled to the memory array and the enabling circuitr for energizing more than one of the plurality of word lines in the memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of the memory array so two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

A semiconductor wafer including at least one integrated circuit memory device comprising:

• a memory array comprising:
• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling repair of the memory array;
• and
• word line energizing circuitry coupled to the memory array and the enabling circuitry for energizing more than one of the plurality word lines in the array in accordance with each row address in response to the enabling circuitry effecting refreshing of the memory array so two or more of the plurality memory cells are accessible through each pair the plurality of pairs of complementary digit lines for each row address.

An electronic apparatus including an input device, an output device, at least one memory device, and a processor device coupled to the input, output, and the at least one memory device, the at least one memory device comprising:

• a plurality of pairs of complementary digit lines;
• a plurality of word lines selectable in accordance with row addresses;
• and
• a plurality of memory cells each memory cell of the plurality of memory cells having a control terminal coupled to one of the plurality of word lines and an access terminal coupled to one of the plurality of pairs of complementary digit lines;
• enabling circuitry for enabling repair of the memory array;
• and
• word line energizing circuitry coupled to the memory array and the enabling circuitry for energizing more than one of the plurality of word lines in the memory array in accordance with each row address in response to the enabling circuitry effecting refreshing of the memory array so that at least two or more of the plurality of memory cells are accessible through each pair of the plurality of pairs of complementary digit lines for each row address.

A method of testing the charging of a memory array of a type to store a bit by storing a charge in a memory cell, the memory array also being a type to access the bit by sharing the stored charge with one of two conductors and then detecting a resulting change in voltage between the one of two conductors, the method comprisin:

• connecting at least two memory cells in a group of memory cells in the memory array to the one of said two conductors;
• storing the electricl charge representing the bit in the at least two memory cells in the group of memory cells in the memory array by each memory cell of the plurality of memory cells storing the charge representing the bit;
• sharing the charge stored in each memory cell of the at least two memory cells in the group of memory cells in the memory array to share its stored charge with the one of the two conductors connected to the at least two memory cells in the group of memory cells in the memory array;
• and
• detecting the change in voltage between the one of two conductors resulting from the at least two memory cells in the group in the group of memory cells in the memory array connected to the one of the two conductors sharing the stored charges in the at least two memory cells in the group of memory cells in the memory array with the one of the two conductors connected thereto.