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US 6,285,612 B1Granted
Reduced bit line equalization level sensing scheme
AssigneeInternational Business Machines Corporation
InventorJohn K. DeBrosse
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorJohn K. DeBrosse
Estimating the term…
A method for obtaining equalization voltages that are a fraction of bit line high other than ½ in a DRAM semiconductor circuit, and an associated circuit, in arrangements that include a plurality of block cell arrays with a plurality of complementary pairs of bit lines connected to each block array with control lines to selectively activate a desired array block. Each block uses shared sense amplifiers connected to the pairs of bit lines and there is an equalization circuit connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit is also connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit control line is connected to the charge flow circuits for connecting the charge flow circuit to an electrical ground, thereby to act as a discharge circuit or to the bit line high voltage. By selecting a number of inactive bit line pairs in a block to be connected to either ground or bit line high voltage the equalization voltage can be readily maintained at a fraction of bit line high voltage other than ½.
A DRAM semiconductor circuit comprising:
A method for obtaining a desired bit line equalization voltage in a dram circuit comprising an active and an inactive block of bit line arrays alternatively connected to shared sense amplifiers, said equalization voltage being a fraction of an applied bit line high voltage Vblh less than ½ Vblh, the method comprising calculating a number of bit line pairs to be discharged by grounding using the following relationship:
A method for obtaining a desired bit line equalization voltage in a dram circuit comprising an active and an inactive block of bit line arrays alternatively connected to shared sense amplifiers, said equalization voltage being a fraction of an applied bit line high voltage Vblh greater than ½ Vblh, the method comprising calculating a number of bit line pairs to be discharged by grounding using the following relationship:
Dependencies are inferred from the claim text.