Method and apparatus for testing memory devices
AssigneeMicron Technology, Inc.
InventorWallace E. Fister
Life of this patent
Estimating the term…
Abstract
A test circuit for functionally testing memory devices. The test circuit loads a plurality of data bits into the memory device under test. The test circuit subsequently reads the data bits stored in the memory cells, and detects if the logic level of the data bits read is the complement of the logic level written. The logic level is detected over a duration during which at least two data bits are read.
Claims16
A test apparatus for testing a first memory device, the first memory device having a plurality of memory cells each of which is structured to store a data bit, one data bit per memory cell, the test apparatus comprising:
- a processor having a processor bus;
- an input device coupled to the processor through the processor bus and structured to allow data to be entered into the test apparatus;
- an output device coupled to the processor through the processor bus and structured to allow data to be output from the test apparatus;
- a second memory device coupled to the processor through the processor bus, the second memory device structured to store a plurality of data bits;
- and
- a test circuit coupled to the processor, the test circuit comprising:
- a memory loader circuit coupled to the first memory device, the memory loader circuit structured to cause a plurality of data bits having a first logic level to be stored in the memory cells;
- a memory reader circuit coupled to the first memory device, the memory reader circuit structured to serially read a plurality of data bits from the memory cells after the memory loader circuit causes the plurality of data bits to be stored in the memory cells, and structured to output a plurality of the data bits read;
- and
- a comparator circuit coupled to the memory reader circuit to receive the plurality of data bits output, the comparator circuit structured to sequentially compare, for a predetermined duration of time, the plurality of data bits output with the first logic level.
A method for testing a memory device, the memory device having a plurality of memory cells for storing a plurality of data bits, the method comprising the steps of:
- conducting a plurality of device cycles to the memory device, each device cycle comprising:
- loading a data bit having a first logic level into a memory cell;
- and
- causing the memory device to output a data bit from a memory cell that was loaded;
- and
- conducting a single tester cycle for each of the plurality of device cycles, each tester cycle comprising detecting if the logic level of a plurality of the data bits output is the first logic level.
Dependencies are inferred from the claim text.