Method and apparatus for using supply voltage for testing in semiconductor memory devices

A method for testing a bitline driver in a memory device, the bitline driver having a data line, the method comprising the steps of:

• providing a programming signal and a supply signal, each suitable for providing power to the memory device, wherein the programming signal is in selectable electrical communication with the data line;
• setting the supply signal to a predetermined value;
• isolating the programming signal from the data line;
• and
• providing the supply signal to the data line.

A method for testing a memory device having a bitline driver, the bitline driver having a corresponding data line, the method comprising the steps of:

• providing a programming signal and a supply signal, wherein the supply signal includes a corresponding supply voltage, wherein the programming signal and supply signal are suitable for powering the memory device, and wherein the programming signal is in selectable electrical communication with the data line;
• setting the supply voltage to a selected value;
• generating a logic signal having a plurality of corresponding voltages each indicative of logic value;
• generally isolating the programming signal from the data line with a selected logic value of the logic signal;
• and
• providing the supply signal to the data line with the selected logic value of the logic signal.

A memory device, the memory device suitable for receiving a programming signal voltage and a supply signal voltage, the memory device comprising:

• a data line, wherein the data line is suitable for selectively receiving the programming signal voltage or the supply signal voltage;
• a supply signal line in selectable electrical communication with the data line and suitable for connection to the supply signal voltage, the supply signal line for providing the supply signal voltage to the data line to stress-test the data line;
• and
• a bitline driver circuit operably coupled to the data line for controlling the supply signal voltage on the data line and for selectively providing the programming signal voltage to the data line in normal operation and for selectively providing the supply signal voltage to the data line in test mode operation.

A memory device, the memory device suitable for receiving a programming signal and a supply signal, the memory device comprising:

• a data line, wherein the data line is suitable for selectively receiving the programming signal;
• a supply signal line in electrical communication with the data line and suitable for connection to the supply signal, the supply signal line for providing the supply signal to the data line;
• a bitline driver circuit operably coupled to the data line for controlling the supply signal on the data line;
• and
• wherein the bitline driver circuit includes a logic circuit for selectively providing one of the programming signal and the supply signal to the data line.

A memory device receiving a power signal and a programming signal, the memory device comprising:

• a plurality of memory cells for storing data therein, the memory cells arranged in memory blocks, wherein the data in each memory block is erased independently and without affecting data in other memory blocks, and wherein at least some of the memory cells are operably coupled to a data line;
• and
• a bitline driver circuit operably coupled to the data line, the power signal, and the programming signal;
• wherein the bitline driver circuit includes a power circuit selectively providing the power signal to the data line.

A memory system, comprising:

• inputs for receiving a programming signal voltage and a supply signal voltage, each suitable for powering at least a portion of the memory system;
• a memory circuit in electrical communication with the programming signal voltage and the supply signal voltage, the memory circuit having:
• a plurality of memory cells operably coupled to a data line;
• a bitline driver circuit operably coupled to the data line, the bitline driver circuit for controlling an electrical signal provided to the data line;
• and
• wherein the supply signal is provided to the data line through the bitline driver circuit in test mode operation of the memory system and the programming signal voltage is provided to the data line through the bitline driver circuit in normal operation of the memory system.