US 6,285,606 B1 · Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device can generate a decoder enable signal (YREDB) that can enable and disable a decoder circuit according to external address signals such that the decoder circuit is enabled when ordinary memory cells are accessed and disabled when redundant memory cells are accessed. The semiconductor memory device may include redundancy circuits (010) that may be placed in a first state when an ordinary memory cell is accessed and in a second state when a redundant memory cell is accessed. A combining circuit can activate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the first state and deactivate the decoder enable signal (YREDB) when the redundancy circuits (010) are in the second state. In addition, a pulse generator (011) can provide an ordinary mode pulse (YRDB) in synchronism with all external clock. An ordinary mode pulse (YRDB) can activate the decoder enable signal (YREDB) when access is switched from a redundant memory cell to an ordinary memory cell.

Claims13

Dependent claims

A semiconductor memory device, comprising:

a plurality of ordinary memory cells;
a plurality of redundant memory cells;
and
a decoder circuit section that accesses ordinary memory cells in response to an address signal received in synchronism with a clock signal, the decoder circuit section being enabled by an active decoder enable signal when ordinary memory cells are accessed, the decoder circuit section being disabled by an inactive decoder enable signal when redundant memory cells are accessed, the decoder enable signal being activated in synchronism with the clock signal when access is switched from a redundant memory cell to an ordinary memory cell.

1 more element

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims13