Semiconductor memory device provided with I/O clamp circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsSusumu Tanida, Yasuhiko Tsukikawa
Life of this patent
Estimating the term…
Abstract
A potential of an I/O line pair is defined at Vcc2−Vth by a clamp circuit, and a clamp voltage is generated by a current mirror circuit including an n channel MOS transistor and p channel MOS transistors and a constant current source. The I/O line pair is thus clamped through p channel MOS transistors connected in series between the I/O line pair.
Claims9
A semiconductor memory device provided with an I/O clamp circuit connected to an I/O line pair for applying an output signal from a sense amplifier to a preamplifier, comprising
- a current mirror circuit for clamping a potential of said I/O line pair at a prescribed potential in an active state.
A semiconductor device provided with an I/O line connecting a first sense amplifier and a second sense amplifier, and connected to a first reference potential and a second reference potential lower than said first reference potential, wherein
- a connecting element and a transistor are connected in series between said I/O line and said second reference potential;
- said transistor has a first electrode connected to said connecting element, a second electrode connected to said second reference potential, and a control electrode connected to a circuit supplying a constant potential to said control electrode;
- and
- when potential of said I/O line exceeds a prescribed potential between said first and second potentials, a current flows from said I/O line through said connecting element and said transistor to said second potential.
A semiconductor device provided with an I/O line connecting a first sense amplifier and a second sense amplifier, and connected to a first reference potential and a second reference potential lower than said first reference potential, comprising
- a circuit causing a current flow from said I/O line to said second reference potential when potential of said I/O line rises from a prescribed potential between said first and second potentials while said semiconductor device is active.
Dependencies are inferred from the claim text.