Semiconductor memory having electrically erasable and programmable nonvolatile semiconductor memory cells

A semiconductor memory having an electrically erasable and programmable nonvolatile semiconductor memory cell, comprising:

• a setting circuit which sets a potential for writing to the cell, the potential corresponding to a level indicated by a bit data string obtained by arranging a plurality of pieces of bit data to be stored in the cell in a predetermined order;
• and
• a discriminating circuit which discriminates the potential set to the cell by the setting circuit based on a reference potential corresponding to the bit data string, wherein
• the discriminating circuit sequentially reads a plurality of pieces of one-bit data constituting the bit data string arranged in the predetermined order from a piece of one-bit data corresponding to a starting bit of the bit data string every time the discriminating circuit performs a discriminating operation with respect to the cell by setting the reference potential to a level corresponding to a number of bits in the bit data string, a number of times of discriminating operations to be performed with respect to the cell and a result of the discriminating operation already performed with respect to the cell, wherein
• in a first discriminating operation with respect to the cell, the discriminating circuit reads data in a starting bit of the bit data string by setting the reference potential to an intermediate level between a potential level corresponding to a minimum level possibly indicated by the bit data string when values set from the starting bit to a so-far-read bit of the bit data string are the read values and a value set to the next to-be-read bit is 1 and values set to other bits are unknown and a potential level corresponding to a maximum level possibly indicated by the bit data string when values set from the starting bit to the so-far-read bit of the bit data string are the read values and a value set to the next to-be-read bit is 0 and values set to the other bits are unknown.

A memory apparatus for storing a plurality of data blocks each provided for a plurality of memory bits, comprising:

• an electrically erasable and programmable nonvolatile semiconductor memory including a plurality of semiconductor memory cells;
• a potential setting circuit which sets one of multi-level potentials to a semiconductor memory cell;
• and
• a memorizing circuit which memorizes a plurality of bits by use of said potential setting circuit, and which assigns a plurality of bits to be memorized in a semiconductor memory cell to a data block of said plurality of data blocks, respectively, to memorize bit data of a plurality of data blocks in a semiconductor memory cell.

A semiconductor memory having an electrically erasable and programmable nonvolatile semiconductor memory cell, comprising:

• a setting circuit which sets a potential for writing to the cell to store at least two bits of information in said cell, the potential corresponding to one of at least four levels indicated by a bit data string of at least two bits obtained by arranging a plurality of pieces of bit data to be stored in the cell in a predetermined order;
• and
• a discriminating circuit which discriminates the potential set to the cell by the setting circuit based on a reference potential corresponding to the bit data string, wherein
• the discriminating circuit sequentially reads a plurality of pieces of one-bit data constituting the bit data string arranged in the predetermined order from a piece of one-bit data corresponding to a starting bit of the bit data string every time the discriminating circuit performs a discriminating operation with respect to the cell by setting the reference potential to a level corresponding to a number of bits in the bit data string, a number of times of discriminating operations to be performed with respect to the cell and a result of the discriminating operation already performed with respect to the cell, wherein
• in a first discriminating operation with respect to the cell, the discriminating circuit reads data in a starting bit of the bit data string by setting the reference potential to an intermediate level between a potential level corresponding to a minimum level possibly indicated by the bit data string when values set from the starting bit to a so-far-read bit of the bit data string are the read values and a value set to the next to-be-read bit is 1 and values set to other bits are unknown and potential level corresponding to a maximum level possibly indicated by the bit data string when values set from the starting bit to the so-far-read bit of the bit data string are the read values and a value set to the next to-be-read bit is 0 and values set to the other bits are unknown.

A memory apparatus for storing a plurality of data blocks each provided for a plurality of memory bits, comprising:

• an electrically erasable and programmable nonvolatile semiconductor memory including a plurality of semiconductor memory cells;
• a potential setting circuit which sets one of at least four levels of potentials to a semiconductor memory cell to store at least two bits of information in said memory cell;
• and
• a memorizing circuit which memorizes a plurality of bits by use of said potential setting circuit, and which assigns a plurality of bits to be memorized in a semiconductor memory cell to a data block of said plurality of data blocks, respectively, to memorize bit data of a plurality of data blocks in a semiconductor memory cell.

A semiconductor memory, comprising:

• an input/output control portion;
• a buffer storing a plurality of data units inputted to said input/output control portion;
• a plurality of nonvolatile semiconductor memory cells;
• and
• a write control portion for forming a plurality of bit data strings of at least two bits by selecting bits having mutually corresponding bit positions of said plurality of data units to set one of at least four potential levels corresponding to said plurality of bit data strings in each of said nonvolatile semiconductor memory cells, respectively to store at least two bits of information in each of said memory cells.

A semiconductor memory, comprising:

• an input/output control portion;
• a buffer storing a plurality of data units inputted to said input/output control portion;
• a plurality of nonvolatile semiconductor memory cells;
• and
• a write control portion for forming a plurality of bit data strings by selecting bits having mutually corresponding bit positions of said plurality of data units to set one of a plurality of potential levels corresponding to said plurality of bit data strings in each of said nonvolatile semiconductor memory cells, respectively.