US 6,285,591 B1 · Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller

Abstract

A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation if the write data. A program controller is provided for writing the data into a selected memory cell in the designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

Claims10

Dependent claims

A method for controlling programming of an electrically erasable and programmable nonvolatile memory having a plurality of memory cells, said nonvolatile memory providing a row and column decoder, address buffer, bit line controller including sense/latch circuit and data {fraction (1/0)} buffer, comprising the steps of:

supplying address signals to said address buffer to define at least one selected memory cell in said plurality of memory cells;
supplying to said bit line controller via said data {fraction (1/0)}buffer programming data which corresponds to a write data to be written in said selected memory cell and latching the programming data in the sense/latch circuit;
writing the write data into the selected memory cell;
reading the written data of said selected memory cell and verifying whether or not the data is successfully written,
performing a logic operation with respect to the read data and said programming data being latched in the sense/latch circuit to determine if the written memory cell is insufficiently written or successfully written,
if an insufficiently written memory cell is found, maintaining the programming data and rewriting the write data into the insufficiently written memory cell,
if the written data is successfully written, modifying latest programming data for the respective successfully written memory cell and stopping to write the data in the successfully written memory cell, and
automatically updating a rewrite data being latched in said/latch circuit in accordance with the verified write state.

5 more elements

A method which controls programming of an electrically erasable and programmable nonvolatile semiconductor memory device including a plurality of bit lines, a plurality of word lines insulatively intersecting said bit lines, a memory cell array formed of electrically erasable and programmable memory cells coupled to said bit lines and said word lines and arranged in a matrix of rows and columns, an a plurality of program circuits including address buffers and row and column decoders which control selection of memory cells, application of write voltages to the selected memory cells and sensing of actual written states of said selected memory cells, comprising the steps of:

storing control data at one of first and second predetermined logic levels which define whether or not write voltages are to be applied to respective of the memory cells selected by said program circuits;
applying said write voltages to said respective memory cells selected by said program circuits in dependence on whether the control data corresponding to the respective of the memory cells is at said first pre-determined logic level or at said second predetermined logic level;
sensing actual written states of only given memory cells for which control data of said first predetermined logic level are stores;
modifying latest stored control data from said first predetermined logic level to said second predetermined logic level for memory cells in which successful writing of data has been sensed;
maintaining said stored control data at said first predetermined logic level for memory cells in which it has been sensed that data has not been successfully written;
and
maintaining said stored control data at said second predetermined logic level upon storing control data at said second predetermined level.

4 more elements

Dependencies are inferred from the claim text.

Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller

Life of this patent

Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller

Life of this patent

Abstract

Claims10