Low power consumption semiconductor ROM, EPROM, EEPROM and like circuit

A low power consumption Read-Only Memory (ROM) circuit comprising:

• a read-only memory (ROM) core with a plurality of intersecting bit lines and word lines and memory cells at predetermined intersections of the bit lines and word lines, each of the memory cells including an NMOS transistor;
• a pre-discharge circuit electrically connected to the ROM core and configured for discharging each of the bit lines to ground;
• a multiplexer (MUX) circuit with an output node, the MUX circuit electrically connected to the pre-discharge circuit and configured for selecting at least one of the bit lines as an input to the MUX circuit;
• and
• a sense amplifier circuit configured for sensing electrical changes in the output node of the MUX circuit and generating current for charging a bit line of the ROM core, the sense amplifier circuit including an input node electrically connected to the output node of the MUX circuit, at least one input reference line and a sense amplifier circuit output node.

A memory comprising:

• a plurality of bit lines;
• a plurality of memory cells connected to the bit lines;
• a multiplexor having a plurality of first terminals connected to the bit lines and a second terminal;
• a discharge circuit having a plurality of discharge transistors connected to the bits lines so that a discharge transistor is continuously connected to each bit line;
• and
• a sense amplifier connected to the second terminal of the multiplexor.

A method for operating a memory, the memory comprising:

• a plurality of bit lines;
• a plurality of memory cells connected to the bit lines, the memory cells being arranged in rows and columns such that each memory cell in a row is connected to a different bit line;
• a multiplexor having a plurality of first terminals connected to the bit lines and a second terminal;
• a discharge circuit having a plurality of discharge transistors connected to the bits lines so that a discharge transistor is connected to each bit line;
• and
• a sense amplifier connected to the second terminal of the multiplexor,
• the method comprising the steps of:
• selecting a row of memory cells;
• selecting a bit line with the multiplexor such that the voltage from only one bit line is coupled to the second terminal of the multiplexor, each bit line having a voltage, a to-be-read memory cell being identified by a selected row of memory cells and a selected bit line;
• pulling down the voltages on the bit lines with the discharge circuit;
• and
• sourcing current into the second terminal of the multiplexor with the sense amplifier after the voltage on the bit lines has been pulled down.