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US 6,285,589 B1Granted
Non-volatile semiconductor memory apparatus
AssigneeSanyo Electric Co., Ltd.
InventorMasanori Kajitani
Life of this patent
Estimating the term…
Abstract
Disclosed is a non-volatile semiconductor memory apparatus, having floating gate electrodes, from which multi-value data can be accurately read out. A memory cell transistor (40) is provided in a row with a plurality of reference transistors (50), and a plurality of such rows are selectively connected by a word line (43). Reference potentials (Va˜Vc) are written to the reference transistors (50) simultaneous to the writing of data to the memory cell transistor (40). In read mode, following the completion of the writing operation, memory data is determined by comparing reference potentials (VR1˜VR3) which have been read out from the reference transistors (50), with a potential (VBL) which has been read out from the memory cell transistor (40).
Claims9
A non-volatile semiconductor memory apparatus, comprising:
- a memory cell transistor, having an insulated floating gate electrode in which a charge is stored, said memory cell transistor varies a resistance thereof, when enabled, in accordance with an amount of charge stored in said floating gate electrode;
- a plurality of reference transistors, having a same structure as said memory cell transistor and being disposed in a row therewith;
- a bit line, which connected to said memory cell transistor;
- a plurality of reference bit lines, which connected to said plurality of reference transistors;
- a write circuit for supplying a common write clock having a predetermined cycle to said memory cell transistor and said plurality of reference transistors, and writing data to said memory cell transistor and said plurality of reference transistors;
- and a controller for detecting the resistances of said memory cell transistor and said plurality of reference transistors during leisure times in the writing operation of said write clock, stopping the supply of said write clock from said write circuit to said memory cell transistor when the detected resistance of said memory cell transistor reaches a purpose value corresponding to write data, and sequentially stopping the supply of said write clock from said write circuit to said plurality of reference transistors when the detected resistances of said plurality of reference transistors have reached a plurality of reference values which are set in steps.
3 more elements
A non-volatile semiconductor memory apparatus, comprising:
- a plurality of memory cell transistors, having insulated floating gate electrodes in which a charge is stored, said memory cell transistors being disposed in rows and columns and varying resistances in accordance with the amount of charge stored in said floating gate electrodes;
- a plurality of reference transistors, having a same structure as said memory cell transistors, a predetermined number of said reference transistors being disposed for each row of said memory cell transistors;
- a plurality of bit lines, which connected to said plurality of memory cell transistors;
- said bit lines being provided along each column of said memory cell transistors;
- a plurality of reference bit lines, which connected to said plurality of reference transistors;
- a write circuit for supplying a common write clock having a predetermined cycle to said memory cell transistor and said plurality of reference transistors, and writing data to said plurality of memory cell transistors and said plurality of reference transistors;
- and a controller for detecting the resistances of said plurality of memory cell transistors and said plurality of reference transistors during leisure times in the writing operation of said write clock, stopping the supply of said write clock from said write circuit to said plurality of memory cell transistors when the detected resistance of said memory cell transistors reach values corresponding to write data, and sequentially stopping the supply of said write clock from said write circuit to said plurality of reference transistors when the detected resistances of said plurality of reference transistors have reached a plurality of reference values which are set in steps;
- wherein
- said plurality of memory cell transistors are divided into separately-operated column units;
- said plurality of reference transistors and said plurality of reference bit lines are arranged in plurality of pairs in accordance with the divisions of said plurality of memory cell transistors;
- and each division unit of said memory cell transistors operates in conjunction with one pair from said plurality of reference transistors and said plurality of reference bit lines.
8 more elements
A non-volatile semiconductor memory apparatus, comprising:
- a memory cell transistor, having an insulated floating gate electrode in which a charge is stored, said memory cell transistor varying in accordance with an amount of charge accumulating at said floating gate electrode;
- a source line, connected to the source of said memory cell transistor;
- a word line, connected to the gate of said memory cell transistor;
- a bit line, connected to the drain of said memory cell transistor;
- a plurality of reference transistors, having the same structure as said memory cell transistor, the sources of said reference transistors being connected to said source line and the gates of said reference transistors being connected to said word line;
- a plurality of reference bit lines, separately connected to the drains of said plurality of reference transistors;
- a source line voltage-controlled circuit, connected to said source line, for supplying a common write clock, having a predetermined cycle, to said memory cell transistor and said plurality of reference transistors during writing thereto;
- a bit line voltage-controlled circuit, for independently controlling potentials of said bit line and said plurality of reference bit lines, and detecting the resistances of said memory cell transistor and said plurality of reference transistors;
- and
- a memory level controller, a plurality of differing reference values corresponding to said plurality of reference transistors being set in steps in said memory level controller,
- wherein, during said reading, which is repeated during leisure times in the writing operation of said write clock, when a resistance of said memory cell transistor, when enabled, has reached a value corresponding to desired write data, said memory level controller stops the writing to the memory cell transistor, and when resistances of said reference transistors have reached said reference values corresponding thereto, said memory level controller stops the writing to said reference transistors.
8 more elements
Dependencies are inferred from the claim text.