Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
AssigneeAdvanced Micro Devices, Inc.
InventorRichard Fastow
Life of this patent
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Abstract
A method to tighten the threshold voltage distribution curve in a memory device during a negative gate source erase by applying 5 volts to the sources of all the memory cells in the memory device, allowing the drains to float and applying a negative pulse followed by a positive pulse to all the control gates of all the memory cells in the memory device. During a negative gate channel erase, the drains and sources are allowed to float, the p-well is biased at plus 5 volts and a negative pulse followed by a positive pulse is applied to all the control gates of all the memory cells in the memory device.
Claims10
A method to tighten the threshold voltage distribution curve in a memory device composed of multiple memory cells each having a source, a drain, a floating gate and a control gate, wherein the memory cells are organized in rows and columns with the rows being wordlines and the columns being bitlines, the method comprising:
- (a) applying a voltage of approximately 5 volts to the sources of all the memory cells;
- (b) allowing the drains of the all the memory cells to float;
- and
- (c) applying a negative voltage pulse followed by a positive voltage pulse to the control gates of all the memory cells, wherein a magnitude of the magnitude of the positive voltage pulse, a length in time of the positive voltage pulse, a length in time of the negative voltage pulse and a length in time between the negative voltage pulse and the positive voltage pulse is determined during a characterization procedure for the memory device.
A method to tighten the threshold voltage distribution curve in a memory device composed of multiple memory cells each having a source, a drain, a floating gate and a control gate, wherein the memory cells are formed in a p-well and are organized in rows and columns with the rows being wordlines and the columns being bitlines, the method comprising:
- (a) applying 5 volts to the p-well;
- (b) allowing the drains and the sources of the memory cells to float;
- (c) applying a negative voltage pulse followed by a positive voltage pulse to the control gates of all the memory cells, wherein a magnitude of the positive pulse, a length in time of the positive voltage pulse, a length in time of the negative voltage pulse and a length in time between the negative voltage pulse and the positive voltage pulse is determined during a characterization procedure for the memory device.
Dependencies are inferred from the claim text.