Nonvolatile static random access memory

A nonvolatile static random access memory adapted for a semiconductor substrate, at least comprising:

• a plurality of nonvolatile static random access memory cell, each nonvolatile static random access memory cell comprising:
• a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain terminal is connected to a first bit line;
• an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line;
• a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal;
• a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal;
• and
• a plurality read control transistor, each read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.

A method for operating a nonvolatile static random access memory (NVSRAM) adapted for a nonvolatile static random access memory, the memory at least comprising:

• a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain terminal is connected to a first bit line;
• an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line;
• a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal;
• a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal;
• and a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line, comprising the step of:
• (1) after power is turned on, the data stored in the charge storage layer of the nonvolatile erasable programmable memory transistor is read out in a nonvolatile operation mode and is transmitted to a data buffer region, and then, the data in the data buffer region is transmitted and stored in the NVSRAM cell in a SRAM operation mode;
• (2) after the data is converted, the NVSRAM cell is operated in SRAM operation mode;
• and
• (3) before power is turned off, the data stored in the NVSRAM cell is read out in SRAM mode and is transmitted to the data buffer region, and then, the data in the data buffer region is stored in the charge storage layer in nonvolatile operation mode.