Output switching implementation for a flash memory device
AssigneeAdvaned Micro Devices, Inc.
InventorsKazuhiro Kurihara, Tien-Min Chen
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Abstract
An output buffer control circuit for a simultaneous operation flash memory device is disclosed. The output buffer control circuit receives signals indicating when an equalization or address transition detect phase of operation is happening and blocks the output enable input signal from reaching the output buffers of the memory device. This prevents the output buffers from switching.
Claims26
An output buffer control circuit for a flash memory device, said circuit comprising:
- a latch operative to be set when an equalization signal is received and be set when an address transition detect signal is received;
- a latch release signal receiver for receiving a latch release signal and to operative to unset said latch upon receipt of said latch release signal;
- and
- an output enable transmission circuit comprising an input for receiving an output enable signal and an output for transmitting said output enable signal and wherein said output enable transmission circuit is coupled with said latch and operative to pass said output enable signal from said input to said output when said latch is unset and block said output enable signal from said input to said output when said latch is set.
An output buffer control circuit for a flash memory device, said device comprising an output enable input, said circuit comprising:
- a buffer controller coupled with said output enable input and responsive to an equalization signal and an address transition detect signal;
- an output buffer coupled with said buffer controller and said output enable input;
- and
- wherein said buffer controller blocks said output enable input to said output buffer when said equalization signal is asserted;
- and
- further wherein said buffer controller blocks said output enable input to said output buffer when said address transition detect signal is asserted.
An apparatus for controlling noise on a flash memory device, said device comprising an output enable input and a data output, said apparatus comprising:
- an output buffer coupled with said output enable input and operative to output data to said data output when said output enable is asserted;
- a buffer controller coupled with said output enable input, said output buffer, and responsive to an equalization signal and an address transition signal;
- said buffer controller being operative to block said output enable input to said output buffer when said equalization signal is asserted;
- and
- said buffer controller further being operative to block said output enable input to said output buffer when said address transition detect signal is asserted;
- whereby electrical noise is reduced during the assertion of said equalization signal and said address transition detect signal.
A method of controlling electrical noise on flash memory device, the method comprising:
- generating an equalization signal;
- generating an address transition detect signal;
- providing an output enable input to an output buffer;
- blocking said output enable input to said output buffer when said equalization signal is generated;
- blocking said output enable input to said output buffer when said address transition detect signal is generated;
- preventing said output buffer from switching due to said blocking;
- and
- reducing noise generated within said flash memory device due to said prevention of switching of said output buffer.
An output buffer control circuit for a flash memory device, said device comprising an output enable input, said circuit comprising:
- a buffer controller responsive to an equalization signal and an address transition detect signal;
- an output buffer responsive to said output enable input;
- and
- wherein said buffer controller prevents said output buffer from switching when said equalization signal is asserted;
- and
- further wherein said buffer controller prevents said output buffer from switching when said address transition detect signal is asserted.
A method of controlling operation of an output buffer in a memory device, the method comprising:
- generating a buffer enable signal when an output enable signal is asserted and a latch is unset, thereby enabling operation of said memory device output buffer;
- setting said latch after said output enable signal is unasserted, thereby preventing generation of said buffer enable signal when said output enable signal is asserted;
- and
- unsetting said latch after said output enable signal is asserted, thereby generating said buffer enable signal.
Dependencies are inferred from the claim text.