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US 6,285,580 B1Granted
Method and apparatus for hardening a static random access memory cell from single event upsets
AssigneesBAE Systems Information, Electronic Systems Integration Inc.
InventorsHo Gia Phan, Derwin Jallice, Bin Li, Joseph Hoffman
Life of this patent
Estimating the term…
Abstract
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
Claims26
A single event upset hardened bi-stable circuit, comprising:
- a first transistor, a second transistor, a third transistor, and a fourth transistor;
- a first isolation transistor connected in series between said third transistor and said fourth transistor to form a first inversion path with said first transistor and said second transistor, wherein a body of said first isolation transistor is connected to a node between said third transistor and said first isolation transistor;
- and
- a second isolation transistor connected in series between said first transistor and said second transistor to form a second inversion path with said third transistor and said fourth transistor, wherein a body of said second isolation transistor is connected to a node between said first transistor and said second isolation transistor.
1 more element
A single event upset hardened bi-stable circuit, comprising:
- a first transistor, a second transistor, and a third transistor connected in series;
- and
- a fourth transistor, a fifth transistor, and a sixth transistor connected in series, wherein a gate of said second transistor and said fifth transistor is connected to ground, wherein a gate of said first transistor is connected to a node between said fourth transistor and said fifth transistor, wherein a gate of said fourth transistor is connected to a node between said first transistor and said second transistor, wherein a gate of said third transistor is connected to a node between said fifth transistor and said sixth transistor, wherein a gate of said sixth transistor is connected to a node between said second transistor and said third transistor, wherein a body of said second transistor is connected to a node between said first transistor and said second transistor, wherein a body of said fifth transistor is connected to a node between said fourth transistor and said fifth transistor.
A memory device, comprising:
- a sense amplifier;
- an addressing circuitry having a row decoder and a column decoder;
- an array of wordlines and complementary bit line pairs, coupled to said sense amplifier and said addressing circuitry;
- a plurality of memory cells located at an intersection of each of said wordlines and said bit line pairs, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
- a first transistor, a second transistor, a third transistor, and a fourth transistor;
- a first isolation transistor connected in series between said third transistor and said fourth transistor to form a first inversion path with said first transistor and said second transistor, wherein a body of said first isolation transistor is connected to a node between said third transistor and said first isolation transistor;
- and
- a second isolation transistor connected in series between said first transistor and said second transistor to form a second inversion path with said third transistor and said fourth transistor, wherein a body of said second isolation transistor is connected to a node between said first transistor and said second isolation transistor.
5 more elements
An apparatus, comprising:
- an electronic system;
- and
- a memory device having a plurality of memory cells, wherein each of said plurality of memory cells has a single event upset hardened bi-stable circuit that includes:
- a first transistor, a second transistor, a third transistor, and a fourth transistor;
- a first isolation transistor connected in series between said third transistor and said fourth transistor to form a first inversion path with said first transistor and said second transistor, wherein a body of said first isolations transistor is connected to a node between said third transistor and said first isolation transistor;
- and
- a second isolation transistor connected in series between said first transistor and said second transistor to form a second inversion path with said third transistor and said fourth transistor, wherein a body of said second isolation transistor is connected to a node between said first transistor and said second isolation transistor.
4 more elements
Dependencies are inferred from the claim text.