Hidden refresh pseudo SRAM and hidden refresh method
AssigneeIndustrial Technology Research Institute
InventorHong-Yi Huang
Life of this patent
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Abstract
A hidden refresh 2P2N pseudo SRAM having an array of memory cells. Each of the memory cells includes a cross-couple latch and two PMOS access transistors. The cross-couple latch are structured with two NMOS transistors which are cross coupled to each other and provided to store a pair of signals. The two NMOS transistors have their sources connected to a negative source voltage, and their drains and gates cross coupled to each other. The two PMOS transistors are controlled by a word line and provided to respectively access the two NMOS transistors of the cross-couple latch and a pair of bit lines. The two PMOS transistors have their sources connected to the pair of bit lines and drains connected to the drains of the two NMOS transistors, respectively.
Claims20
A hidden refresh psuedo SRAM having a plurality of memory cells, each of the memory cells comprises:
- a cross-couple latch comprising two NMOS transistors cross coupled to each other;
- two PMOS load transistors having their gates connected to an external positive source voltage, their sources connected to an external operating voltage, and their drains connected to a source of the cross-couple latch;
- and
- two PMOS access transistors, controlled by a word line, respectively accessing the two NMOS transistors of the cross-couple latch, the two PMOS load transistors, and a pair of bit lines.
A hidden refresh method for a pseudo SRAM, comprising the steps of:
- providing a pseudo SRAM comprising a plurality of memory cells, each of the memory cells having a cross couple latch which comprises two NMOS transistors cross coupled to each other, two PMOS load transistors having their gates connected to an external positive source voltage, their sources connected to an external operating voltage, and their drains connected to a source of the cross-couple latch;
- and two PMOS access transistors, which are controlled by a word line, respectively accessing the two NMOS transistors of the cross couple latch, the two PMOS load transistors, and a pair of bit lines;
- and
- driving the pair of bit lines to a first voltage, which is higher than a positive source voltage of the pseudo SRAM by a voltage difference when the word line is driven to the positive source voltage.
Dependencies are inferred from the claim text.