Nonvolatile ferroelectric memory

A nonvolatile ferroelectric memory comprising:

• a cell array unit having a first and second reference bitlines, and a plurality of main bitlines on one side of the reference bitlines that extend along a first direction, and a plurality of pairs of first and second split wordlines that extend in a second direction crossing the bitlines;
• a first equalizer under the cell array unit that equalizes adjacent bitlines among odd numbered main bitlines and the first reference bitline;
• a first precharge level adjustor that adjusts levels of the odd numbered bitlines and the first reference bitline in response to a first precharge control signal and a second precharge control signal;
• a first sense amplifier that senses and amplifies signals on the odd numbered bitlines;
• a first reference level generator that receives amplifies a signal on the first reference bitline and provides a result as a reference signal for the first sense amplifier;
• a second equalizer over the cell array unit that equalizes adjacent bitlines among even numbered main bitlines and the second reference bitline;
• a second precharge level adjustor that adjusts levels of the even numbered bitlines and the second reference bitline in response to the first precharge control signal and the second precharge control signal;
• a second sense amplifier that senses and amplifies signals on the even numbered bitlines;
• and
• a second reference level generator that amplifies a signal on the second reference bitline and provides a result as a reference signal to the second sense amplifier.

A memory device having a cell array with at least one reference bitline and a plurality of main bitlines that extend along a first direction, and a plurality of wordlines that extend along a second direction to cross the bitlines, a decoder coupled to the bitlines, a driving circuit coupled to the wordlines, and a sense amplifier that senses signals on the main bitlines, the improvement comprising:

• a precharge level adjustor that adjusts a precharge level of the bitlines in response to a combination of the first precharge control signal and a second precharge control signal, wherein the precharge supply signal generator comprises,
• a transition generator that detects a pad signal to generate a transition detection signal,
• an enable adjustor that receives the transition detection signal and provides a first enable signal and a second enable signal,
• a reference signal forwarding unit enabled in response to the first enable signal to provide a precharge reference signal,
• a precharge level comparator enabled in response to the second enable signal to compare the precharge reference signal to a feedback control signal,
• a precharge level generator controlled by a driving signal from the precharge level comparator that outputs the feedback control signal, and
• a first precharge control signal forwarding unit that receives a supply signal from the precharge level generator to provide the first precharge control signal.

A memory device having a cell array with at least one reference bitline and a plurality of main bitlines that extend along a first direction, and a plurality of wordlines that extend along a second direction to cross the bitlines, a decoder coupled to the bitlines, a driving circuit coupled to the wordlines, and a sense amplifier that senses signals on the main bitlines, the improvement comprising:

• a reference level generator that receives a reference bitline signal and forwards a reference voltage for the sense amplifiers, wherein the reference level generator comprises,
• a first comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an output signal,
• a second comparing and amplifying unit that compares the reference bitline signal to a signal fed back thereto, and amplifies an signal,
• a reference output adjusting unit that adjusts a level of the reference signal in response to the output signals from the first and second comparing and amplifying units,
• a reference output buffer that buffers the adjusted reference signal in the reference output adjusting unit,
• a reference output precharge adjusting unit that adjusts a precharge level of the reference bitline to a precharge level of a main bitline in response to a first precharge control signal and the transition detection signal,
• a first enable adjusting unit that enables the first comparing and amplifying unit, and
• a second enable adjusting unit that enables the second comparing and amplifying unit.