Shadow RAM cell and non-volatile memory device employing ferroelectric capacitor and control method therefor
AssigneeNEC Corporation
InventorTohru Miwa
Life of this patent
Estimating the term…
Abstract
A shadow RAM cell and a non-volatile memory employing a ferroelectric capacitor, and a control method therefor can reduce number of transistors forming a memory cell to permit increasing of capacity comparable with SRAM. The a memory cell includes a flip-flop having a pair of storage nodes, a pair of switching elements controlled ON and OFF by a common word line and controlling connection between a pair of storage nodes and a pair of bit lines, and a pair of ferroelectric capacitors directly connected to the pair of storage nodes at respective one ends and connected to a plate line at the other end.
Claims23
A memory cell comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end.
A memory cell comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end,
- wherein said flip-flop includes a pair of logic inverting elements with respective inputs and outputs connected with each other in said pair of storage nodes,
- wherein each of said logic inverting elements includes one transistor, each of said pair of switching elements includes a single transistor, and said memory cell includes four transistors and said pair of ferroelectric capacitor elements.
A memory cell comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end,
- wherein said plate line is switched between a ground potential and a power source potential while maintaining said pair of switching elements at an OFF state during a storing operation.
A memory cell comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end,
- wherein a power source of said flip-flop is drawn up to a predetermined operation power source potential from a ground potential while maintaining said pair of switching element OFF and maintaining said plate line at ground potential during a recalling operation.
A memory cell comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end,
- wherein a potential of said plate line is set at a predetermined potential between a ground potential and a power source potential while power is supplied except for a storing and a recalling condition.
A non-volatile semiconductor memory device including memory cells arranged in a matrix at each intersection of at least a pair of bit lines and at least a word line, said memory cells comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end.
A non-volatile semiconductor memory device including memory cells arranged in a matrix at each intersection of said pair of bit line and said word line, said memory cells comprising:
- a flip-flop having a pair of storage nodes;
- a pair of switching elements controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines;
- and
- a pair of ferroelectric capacitors each directly connected to said pair of storage nodes at one respective end and connected to a plate line at the other end,
- wherein in all of said memory cells, said plate line is connected in common,
- which further comprises a plate line driving circuit driving said plate line connected in common.
A method for controlling a memory cell including a flip-flop having a pair of storage nodes, a pair of switching element controlled ON and OFF by a common word line and controlling a connection between said pair of storage nodes and a pair of bit lines, and a pair of ferroelectric capacitor elements connected to said pair of storage nodes at respective one ends and to a plate line at the other end, comprising a step of:
- upon initiation of a storing operation, changing said plate line between a ground potential and a power source potential while maintaining said pair of switching element at an OFF state.
Dependencies are inferred from the claim text.