Stress-follower circuit configuration

An integrated circuit comprising:

• a stress-follower circuit configuration;
• the stress-follower circuit configuration being coupled to a pad of said integrated circuit;
• the stress-follower circuit configuration being coupled so as to reduce the voltage stress on an isolation layer of a transistor in a transistor stack so that in operation the transistor in the stack tolerates approximately 1.5 volts above its nominal voltage;
• the transistor stack being coupled to the pad;
• wherein the stress-follower circuit configuration comprises at least three vertical drain rietal-oxide semiconductor field effect transistors (VDMOS transistors);
• said integrated circuit further comprising a voltage bias applied to the gate of the ansistor of the stack that is directly coupled to the pad;
• one of the VDMOS transistors coupling the pad to the voltage bias, the one VDMOS insistor having another voltage bias applied to its gate;
• the remaining VDMOS transistors being coupled together, each in a diode configuration, and also coupling the pad to the voltage bias.