US 6,285,403 B1 · Data slice circuit for slicing data carried on a video signal and a method thereof

Abstract

A data slice circuit to separate data carried on a video signal only at a line on which the data is carried and a method thereof. The circuit includes a top peak detector to detect a top peak of an input video signal to generate a top peak detection signal and a bottom peak detector to detect a bottom peak of the video signal to generate a bottom peak detection signal. A composite synchronous signal separation circuit separates a composite synchronous signal from the video signal, and a clock run-in window circuit generates a first control signal for a clock run-in interval. A sampling/holding circuit samples an intermediate value between the top peak detection signal and the bottom peak detection signal in response to the first control signal of a first state, and holds the sampled intermediate value to generate a reference voltage in response to the first control signal of a second state. A second control signal generator receiving the composite synchronous signal generates a second control signal indicating a line on which data is carried, and a comparator circuit compares the video signal with the reference signal in response to the second control signal. Therefore, the data slice circuit performs a data slice operation only at the line on which the data is carried.

Claims20

Dependent claims

A data slice circuit to perform a data slice operation on an input video signal, comprising:

a top peak detector to detect a top peak of an input video signal to generate a top peak detection signal;
a bottom peak detector to detect a bottom peak of said input video signal to generate a bottom peak detection signal;
a composite synchronous signal separation circuit to separate a composite synchronous signal from said input video signal;
a clock run-in window circuit to generate a first control signal for a clock run-in interval based upon said composite synchronous signal;
a sampling/holding circuit to sample an intermediate value between said top peak detection signal and said bottom peak detection signal in response to said first control signal of a first state, and holding the sampled intermediate value to generate a reference voltage in response to said first control signal of a second state;
a control signal generator to receive said composite synchronous signal and, in response, generate a second control signal indicating a line on which data of the input video signal is being carried;
and
a comparator circuit to compare said input video signal with said reference signal in response to said second control signal;
whereby the data slice circuit performs the data slice operation at the line on which the data is carried.

6 more elements

A data slice circuit to separate data carried on a video signal, comprising:

a slice operation unit to separate the data carried on the video signal based on a clock run-in control signal;
and
a control unit to enable operation of said slice operation unit at a line on which the data of the video signal is carried, based on composite and vertical synchronous signals of the video signal.

A data slice circuit to separate data carried on a video signal, comprising:

a slice operation unit to separate the data carried on the video signal, said slice operation unit generates a composite synchronous signal from the video signal;
and
a control unit to enable operation of said slice operation unit at a line on which the data of the video signal is carried;
wherein said control unit has
a vertical synchronous signal separator to separate a vertical synchronous signal from the composite video signal, and
a line counter to count the composite synchronous signal after the vertical synchronous signal, and to generate a control signal at a predetermined count value of the composite synchronous signal until a next composite synchronous signal is generated subsequent to the predetermined count value, said control signal enabling the operation of said slice operation unit, and said line counter having a counter to count the composite synchronous signal and to be reset by the vertical synchronous signal and a decoder to change a state of said control signal upon the counting of said counter to the predetermined count value;
wherein said counter has
a plurality of D flip-flops each having an input terminal D, a clock terminal, an output terminal Q, an output terminal /Q and a reset terminal /R,
wherein said decoder has
an AND gate,
an inverter,
a first OR gate, and
a second OR gate;
and
wherein each of the reset terminals /R is connected to said vertical synchronous signal separator to receive the vertical synchronous signal, each of the Q output terminals of said plurality of D flip-flops except a last one is connected to the clock terminal of a following one, each input terminal D is connected to the output terminal /Q of the same D flip-flop and either said AND gate or said first OR gate, and the clock terminal of the first D flip-flop is connected to said slice operation unit to receive the composite synchronous signal from said slice operation unit, said AND gate performing an AND operation on signals received from the output terminals /Q connected thereto to generate a first logic signal, said OR gate performing a first OR operation on signals received from the output terminals /Q connected thereto to generate a second logic signal, said inverter inverting the first logic signal to generate an inverted first logic signal, and said second OR gate performing a second OR operation on the inverted first logic signal and the second logic signal to generate the control signal.

12 more elements

A data slice circuit to separate data carried on a video signal, comprising:

a slice operation unit to separate the data carried on the video signal;
and
a control unit to enable operation of said slice operation unit at a line on which the data of the video signal is carried;
wherein the control unit has
a top peak detector to detect a top peak of the video signal, to generate a top peak signal,
a bottom peak detector to detect a bottom peak of the video signal, to generate a bottom peak signal,
a composite synchronous signal separation circuit to separate a composite synchronous signal from the video signal,
a clock run-in window circuit to generate a first control signal for a clock run-in interval based upon the composite synchronous signal,
an intermediate signal generator to generate an intermediate signal from the top and bottom peak signals,
a sampling/holding circuit to sample the intermediate signal in response to the first signal being in a first state and to hold the intermediate signal in response to the first control signal being in a second state, to generate a reference signal,
a vertical synchronous signal separator to separate a vertical synchronous signal from the composite video signal,
a comparator unit to compare the video signal with the reference signal, and
a line counter to count the composite synchronous signal after the vertical synchronous signal, and to generate a second control signal at a predetermined count value of the composite synchronous signal until a next composite synchronous signal is generated subsequent to the predetermined count value, said second control signal enabling the operation of said slice operation unit, and said line counter having a counter to count the composite synchronous signal and to be reset by the vertical synchronous signal and a decoder to change a state of said control signal upon the counting of said counter to the predetermined count value;
wherein said counter has
a plurality of D flip-flops each having an input terminal D, a clock terminal, an output terminal Q, an output terminal /Q and a reset terminal /R,
wherein said decoder has
an AND gate,
an inverter,
a first OR gate, and
a second OR gate, and
wherein each of the reset terminals /R is connected to said vertical synchronous signal separator to receive the vertical synchronous signal, each of the Q output terminals of said plurality of D flip-flops except a last one is connected to the clock terminal of a following one, each input terminal D is connected to the output terminal /Q of the same D flip-flop and either said AND gate or said first OR gate, and the clock terminal of the first D flip-flop is connected to said composite synchronous signal separation circuit to receive the composite synchronous signal, said AND gate performing an AND operation on signals received from the output terminals /Q connected thereto to generate a first logic signal, said OR gate performing a first OR operation on signals received from the output terminals /Q connected thereto to generate a second logic signal, said inverter inverting the first logic signal to generate an inverted first logic signal, and said second OR gate performing a second OR operation on the inverted first logic signal and the second logic signal to generate the second control signal;
and
wherein said control unit enables said comparator unit at the line on which the data of the video signal is carried.

20 more elements

A data slice circuit to separate data carried on a video signal, comprising:

a slice operation unit to separate the data carried on the video signal;
and
a control unit to enable operation of said slice operation unit at a line on which the data of the video signal is carried;
wherein the control unit has
a top peak detector to detect a top peak of the video signal, to generate a top peak signal,
a bottom peak detector to detect a bottom peak of the video signal, to generate a bottom peak signal,
a composite synchronous signal separation circuit to separate a composite synchronous signal from the video signal,
a clock run-in window circuit to generate a first control signal for a clock run-in interval based upon the composite synchronous signal,
an intermediate signal generator to generate an intermediate signal from the top and bottom peak signals,
a sampling/holding circuit to sample the intermediate signal in response to the first signal being in a first state and to hold the intermediate signal in response to the first control signal being in a second state, to generate a reference signal, and
a comparator unit to compare the video signal with the reference signal;
wherein said comparator has
a resistor having a first end to receive a predetermined voltage and a second end,
a first transistor having a base to received the video signal, a collector and an emitter,
a second transistor having a base to receive the reference signal, an emitter connected to the emitter of said first transistor and a collector,
a third transistor having a base, a collector connected to the base and an emitter connected to the predetermined voltage,
a fourth transistor having a based connected to the base of said third transistor an emitter connected to the predetermined voltage and a collector,
a fifth transistor having an emitter connected to the predetermined voltage, a base and a collector connected to the base and the emitter of said second transistor,
a sixth transistor having a base connected to the base of the fifth transistor, an emitter connected to the predetermined voltage and a collector,
a seventh transistor having a collector connected to the emitters of the first and second transistors, a collector connected to another predetermined voltage and a base,
an eighth transistor having an emitter connected to the another predetermined voltage, a collector connected to the emitter of the sixth transistor and a base connected to the collector thereof,
a ninth transistor having a base connected to the base of the eighth transistor, an emitter connected to the another predetermined voltage and a collector connected to the emitter of the fourth transistor,
a tenth transistor having an emitter connected to the another predetermined voltage, and a base and collector connected to the second end of the resistor, and
an eleventh transistor having a base to receive the second control signal, an emitter connected to the another predetermined voltage and a collector connected to the collector of the tenth transistor and the second end of the resistor;
and
wherein said control unit enables said comparator unit at the line on which the data of the video signal is carried.

23 more elements

Dependencies are inferred from the claim text.

Data slice circuit for slicing data carried on a video signal and a method thereof

Life of this patent

Data slice circuit for slicing data carried on a video signal and a method thereof

Life of this patent

Abstract

Claims20