Circuits and methods for functional processing of delta modulated pulse density stream

A signal processor, comprising:

• a Delta Adder (DA) for receiving digital Delta Modulated signals, Xn and Yn, and for producing a pulse density digital output signal, Sn, representing a digital sum of the modulated inputs, Xn, and Yn;
• a shift register connected to receive said pulse density digital stream, Sn, to memorize a past of the signal Sn;
• a programmable detection logic circuit connected to receive outputs of said shift register to form a pulse density stream, F(·);
• a binary full-adder connected to receive the pulse density stream, F(·), and an output from a binary multiplier to add said pulse density stream, F(·), and said output from the binary multiplier to produce a binary output, En+1;
• a D flip-flop to receive the binary signals En+1 and to produce an output, En;
• a binary multiplier to multiply said output En produced by D flip-flop and constant (1−L), wherein L is a scaling constant which depends on the function to be realized and the length of the shift register;
• and a low pass filter connected to receive the binary signal En+1 to produce a predetermined output function f(x,y).