Digital clock recovery loop

A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method comprising:

• using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal;
• extracting a clock from an input digital signal;
• and
• performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

A communications method for extracting a clock signal from incoming digital data using a clock recovery circuit configured as a phase lock loop, the method comprising:

• producing an output wave using a voltage controlled oscillator having a control node and having an output at which the output wave is produced, wherein the output wave has a frequency that varies in response to a voltage applied to the control node;
• controlling the rate of change of the voltage on the control node of the voltage controlled oscillator;
• performing frequency discrimination and adjusting the voltage on the control node of the voltage controlled oscillator;
• performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator;
• and
• applying an offset voltage to the voltage controlled oscillator such that, in operation, in the absence of any voltage applied to the control node, the frequency of the output wave produced by the voltage controlled oscillator is at least half and not greater than the final frequency lock frequency of the voltage controlled oscillator.

A clock recovery method for extracting a clock signal from an input digital signal in a phase lock loop, the method comprising:

• producing, with a voltage controlled oscillator having a control node, an output wave having a frequency that varies in response to a voltage applied to the control node;
• controlling, with charge pump and loop filter circuitry, the rate of change of the voltage on the control node of the voltage controlled oscillator;
• performing, with start-up circuitry, frequency discrimination and, in conjunction with the charge pump and loop filter circuitry, adjusting the voltage on the control node of the voltage controlled oscillator;
• and
• performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.