Phase-locked loop having circuit for synchronizing starting points of two counters

A phase-locked loop circuit comprising:

• a source for producing a reference-frequency signal;
• a first counter for dividing down said reference-frequency signal and producing a first output signal;
• a voltage-controlled oscillator (VCO) circuit for producing a VCO output signal;
• a second counter for dividing down said VCO output signal and producing a second output signal;
• a phase comparator circuit for comparing the phase of said first and second output signals, said phase comparator circuit producing a first error signal when the phase of said second output signal lags the phase of said first output signal, said first error signal having a pulse width corresponding to the lag in phase,
• said phase comparator circuit producing a second error signal when the phase of said second output signal leads the phase of said first output signal, said second error signal having a pulse width corresponding to the lead in phase;
• a charge pump circuit driven by said first and second error signals;
• a low-pass filter for converting an output from said charge pump circuit into a control voltage applied to said VCO circuit;
• and
• a control circuit for resetting said first counter when said phase of said second output signal lags the phase of said first output signal and for resetting said second counter when said phase of said second output signal leads the phase of said first output signal.