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US 6,285,246 B1Granted
Low drop-out regulator capable of functioning in linear and saturated regions of output driver
AssigneeCalifornia Micro Devices Corporation
InventorSudip Basu
Life of this patent
Estimating the term…
Abstract
A low drop-out regulator and methods for producing a low drop-out voltage are provided. A driver transistor adapted for connecting to an input supply voltage and producing an output voltage is provided. In addition, a mirroring transistor is coupled to the driver transistor and a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor. The low drop-out regulator operates in both linear and saturation regions of the driver transistor. The driver transistor and the mirroring transistor are implemented in a CMOS process.
Claims12
A low drop-out regulator, comprising:
- a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain, wherein a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor, wherein the drain of the driver transistor is coupled to the output voltage, and wherein the driver transistor and the mirroring transistor are each implemented as a P-channel MOS transistor;
- and
- a mirroring circuit adapted for sensing a voltage at the drain of the driver transistor and forcing a voltage at the drain of the mirroring transistor equal to the sensed voltage that includes,
- a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor,
- a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate,
- a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor,
- a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor, and
- a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain, wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors.
6 more elements
A low drop-out regulator, comprising:
- a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain, wherein a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor, wherein the drain of the driver transistor is coupled to the output voltage, wherein the driver transistor and the mirroring transistor are each implemented as a PMOS transistor, wherein a voltage differential between the gate and the source is identical for the mirroring transistor and the driver transistor, and wherein the gate of the driver transistor is coupled to the gate of the mirroring transistor, and the source of the driver transistor and the source of the mirroring transistor are coupled to the input supply voltage;
- and
- a mirroring circuit adapted for sensing a voltage at the drain of the driver transistor and forcing a voltage at the drain of the mirroring transistor equal to the sensed voltage, wherein the mirroring circuit includes,
- a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor,
- a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate,
- a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor,
- a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor, and
- a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain, wherein the first transistor and the fourth transistor are identical in size and the second transistor, the third transistor, and the fifth transistor are identical in size, wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors, and wherein the mirroring transistor and the mirroring circuit produce a mirrored current proportional in size to the first, second, third, fourth, and fifth transistors.
6 more elements
A method for providing a low drop-out regulator, comprising:
- providing a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- providing a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain;
- ensuring that a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor, wherein the driver transistor and the mirroring transistor are each implemented as a P-channel MOS transistor;
- sensing the output voltage at the driver transistor;
- mirroring the voltage differential between the drain and the source of the driver transistor in the mirroring transistor;
- coupling the drain of the driver transistor to the output voltage;
- sensing a voltage at the drain of the driver transistor;
- forcing a voltage at the drain of the mirroring transistor equal to the sensed voltage;
- coupling the source of the driver transistor and the source of the mirroring transistor to the input supply voltage;
- coupling the drain of the driver transistor to the output voltage;
- providing a mirroring circuit having an input coupled to the drain of the driver transistor and an output coupled to the drain of the mirroring transistor, the mirroring circuit adapted for sensing the output voltage at the input of the mirroring circuit and placing the sensed output voltage at the output of the mirroring circuit, wherein providing the mirroring circuit includes,
- providing a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor;
- providing a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate;
- providing a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor;
- providing a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor;
- providing a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain;
- and wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors, and
- providing an output buffer coupled to the drain of the fifth transistor and the gates of the driver and the mirroring transistors.
15 more elements
A method for providing a low drop-out regulator, comprising:
- providing a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- providing a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain, wherein the driver transistor and the mirroring transistor are each implemented as a PMOS transistor;
- ensuring that a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor;
- coupling the source of the driver transistor and the source of the mirroring transistor to the input supply voltage;
- coupling the drain of the driver transistor to the output voltage;
- and
- providing a mirroring circuit having an input coupled to the drain of the driver transistor and an output coupled to the drain of the mirroring transistor, the mirroring circuit adapted for sensing the output voltage at the input of the mirroring circuit and placing the sensed output voltage at the output of the mirroring circuit, wherein providing the mirroring circuit includes:
- providing a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor;
- providing a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate;
- providing a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor;
- providing a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor;
- and
- providing a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain;
- wherein the first transistor and the fourth transistor are identical in size and the second transistor, the third transistor, and the fifth transistor are identical in size;
- wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors.
12 more elements
A low drop-out regulator, comprising:
- a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- and
- a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain, wherein a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor, wherein the driver transistor and the mirroring transistor are each implemented as a P-channel MOS transistor, and wherein the source of the driver transistor and the source of the mirroring transistor are coupled to the input supply voltage and the drain of the driver transistor is coupled to the output voltage;
- and
- a mirroring circuit having an input coupled to the drain of the driver transistor and an output coupled to the drain of the mirroring transistor, the mirroring circuit adapted for sensing the output voltage at the input of the mirroring circuit and placing the sensed output voltage at the output of the mirroring circuit that includes,
- a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor;
- a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate;
- a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor;
- a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor;
- a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain;
- wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors.
8 more elements
A low drop-out regulator, comprising:
- a driver transistor adapted for connecting to an input supply voltage and producing an output voltage;
- a mirroring transistor coupled to the driver transistor, the driver transistor and the mirroring transistor being implemented in a CMOS process and each having a gate, a source, and a drain, wherein a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor, wherein the driver transistor and the mirroring transistor are each implemented as a P-channel MOS transistor, and wherein the source of the driver transistor and the source of the mirroring transistor are coupled to the input supply voltage and the drain of the driver transistor is coupled to the output voltage;
- and
- a mirroring circuit having an input coupled to the drain of the driver transistor and an output coupled to the drain of the mirroring transistor, the mirroring circuit adapted for sensing the output voltage at the input of the mirroring circuit and placing the sensed output voltage at the output of the mirroring circuit that includes,
- a first CMOS transistor having a source coupled to the drain of the driver transistor, a drain, and a gate coupled to the drain of the first transistor;
- a second CMOS transistor having a drain coupled to the drain of the first transistor, a source coupled to ground, and a gate;
- a third CMOS transistor having a gate coupled to the gate of the second transistor, a source coupled to the ground, and a drain coupled to the gate of the third transistor;
- a fourth CMOS transistor having a drain coupled to the drain of the third transistor, a source coupled to the drain of the mirroring transistor, and a gate coupled to the gate of the first transistor;
- a fifth CMOS transistor having a source connected to the ground, a gate connected to the gate of the third transistor, and a drain;
- wherein the second, third, and fifth transistors are N-channel MOS transistors and the first and fourth transistors are P-channel MOS transistors.
7 more elements
Dependencies are inferred from the claim text.